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FDCAN PB6 problem with low state under reset on STM32G474

Wasilewski.Piotr
Associate III

Hello, 

I'm experiencing a problem with PB6 pin on STM32G474 MCU when any type of reset occurs. The pin goes low for the whole duration of the reset pin being low, and stays low to around when the FDCAN is initalized. This is a significant issue, as it causes error frames to be sent whenever such device is restarted while connected to a working CAN bus. 

I thought it might be linked to the UCPD Dead battery feature (UCPD1_CC1) - indeed a fresh project without the HAL_PWREx_DisableUCPDDeadBattery(); does not pull the PB6 pin low, however adding this call causes the low state to occur while under reset. The same goes when a FDCAN init is used. It looks as if whatever peripheral touched the PB6 the problem shows up. 

Did anyone experienced anything like this? 

 

1 ACCEPTED SOLUTION

Accepted Solutions
FBL
ST Employee

Hello @Wasilewski.Piotr 

During reset, the ultimate solution would be to pull down PA9 by HW.

FBelaid_0-1707819172515.png

PB4_PUPEN OB is only considered for category 4 devices.

To give better visibility on the answered topics, please click on Accept as Solution on the reply which solved your issue or answered your question.


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6 REPLIES 6
FBL
ST Employee

Hello @Wasilewski.Piotr 

 

Is it possible to reproduce using reference board nucleo or eval and simple loopback example FDCAN? If not, could you check the surrounding circuitry in the layout.

To give better visibility on the answered topics, please click on Accept as Solution on the reply which solved your issue or answered your question.


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Happy New Year!

Sure - the only thing I have to do to reproduce is run an empty project with FDCAN2 remapped to PB5 and PB6. 

I noticed the problem is directly linked to PA9 state during reset - when it's low the problem is nonexistent. However when a small pullup is applied (for example input pullup of a logic analyzer) the PB6 pin mimics the reset pin.

WasilewskiPiotr_1-1706517595565.png

WasilewskiPiotr_2-1706517624295.png

I also attach the project for Nucleo-G474RE.

 

 

Hello, 

was it possible to reproduce the issue on your side @FBL ?

Best Regards

FBL
ST Employee

Hi @Wasilewski.Piotr 

Note 6 in datasheet explains the behavior:

After reset, a pull-down resistor (Rd = 5.1kΩ from UCPD peripheral) can be activated on PB6, PB4 (UCPD1_CC1,
UCPD1_CC2). The pull-down on PB6 (UCPD1_CC1) is activated by high level on PA9 (UCPD1_DBCC1).

 

Workaround:

The pull-down effect on the CC lines can be removed by using the bit UCPD1_DBDIS =1 (USB Type-C and power delivery dead battery disable) in the PWR_CR3 register.

I hope this helps

To give better visibility on the answered topics, please click on Accept as Solution on the reply which solved your issue or answered your question.


I'm out of offce with limited access to my emails.
Happy New Year!
Wasilewski.Piotr
Associate III

Hello, 

So the UCPD1_DBDIS =1 does not help, as the behavior is present during reset. You can see that the pin goes high only after some time, so I don't think it is something that can be solved by software (except maybe some option bytes?). 

FBL
ST Employee

Hello @Wasilewski.Piotr 

During reset, the ultimate solution would be to pull down PA9 by HW.

FBelaid_0-1707819172515.png

PB4_PUPEN OB is only considered for category 4 devices.

To give better visibility on the answered topics, please click on Accept as Solution on the reply which solved your issue or answered your question.


I'm out of offce with limited access to my emails.
Happy New Year!