Double buffered DMA on SAI_I2s_tx CT/TC conflict

[SeyyedMohammad]

I'm running tx and rx of SAI_I2S by double buffered DMA.

I expect on double buffered DMA to change Current Target or CT register bit state to change at each Transfer Complete or TC. But on tx DMA stream it changes CT, one sample before TC. Why?

 But in rx the behaviour is normal, CT changes on TC trigger.

I've seen them by constantly monitoring their register:

while(1)
	{
		if((DMA1->LISR & DMA_LISR_TCIF0)==0)
		{
		test1_GPIO_Port->BSRR=test1_Pin << GPIO_NUMBER;
		}
		else
		{
		test1_GPIO_Port->BSRR=test1_Pin;
		}
 
		if((DMA1_Stream0->CR & DMA_SxCR_CT)==0)
		{
		test_GPIO_Port->BSRR=test_Pin << GPIO_NUMBER;
		}
		else
		{
		test_GPIO_Port->BSRR=test_Pin;
		}
	}

 And the TC is surving by MDMA.

The MCU is STM32H743VIT6.

The FIFO settings fot both tx/rx are set to empty, according to darasheet this must has been disabled FIFO effectively.

[LCE]

Maybe it is FIFO related?

Have you checked if the TX I2S output signal is actually okay or missing a sample?

[waclawek.jan · Accepted solution]

Nice observation.

> one sample before TC.

CT probably flips when the last memory-side transfer is finished, whereas TC sets when the peripheral-side transfer is done.

My tip is, that you have FIFO off, and that FIFO on would make this effect more pronounced. But I may be also wrong in this guess.

JW

[SeyyedMohammad]

Thnks for insight.