Hi everyone,
I’m working with an STM32L5 USART and trying to clarify a point about parity vs. MSB-first transmission.
From the reference manual (USART parity control / frame formats), when parity is enabled the frame formats are shown as:
M=00, PCE=1: SB | 7-bit data | PB | STB
M=01, PCE=1: SB | 8-bit data PB | STB
and there is a note that “in the data register, the PB is always taking the MSB position (8th or 7th depending on M)”.
This wording caused confusion in our class:
one interpretation is that because parity occupies the MSB position in the data register/word length, it might be transmitted before the data bits when MSBFIRST=1.
My understanding is:
MSBFIRST only reverses the order of the data bits inside the data field.
The parity bit remains the parity field in the frame, i.e. logically after the data field and before stop bits.
The “MSB position” note refers to the bit slot within the word length/data register, not to the time order on the line.
Could someone confirm:
Question:
When MSBFIRST is enabled or disabled, does the parity bit position in the transmitted frame change?
Or is it always the same frame structure (SB → data bits (order depends on MSBFIRST) → PB → stop)?
If possible, a short explanation referencing how the hardware maps parity into TDR/RDR vs. the actual serial bit timing would be very helpful.
Thanks!
