DMA behaviour on STM32F072 and STM32F745: Memory consistency

[Christian Wächter]

Hello,

I'm currently working on a UART communication between the mentioned STM32 microcontrollers and would like to use DMA. But I'm a bit concerned about memory consistency. I already read a lot about this issue and tried to find any information, how this is done in the STM32 MCUs, but could not yet find the right thing I'm looking for.

How do the DMA controllers in these MCUs prevent memory corruption or inconsistencies because of simultanious read and write access? Is there a shadow register in the background? Or any hardware logic to prevent the CPU from writing/reading to the memory, when the DMA is doing so?

Thank you and best regards,

Christian

[Tesla DeLorean]

The accesses are interleaved/arbitrated, so they don't "occur at the same time"

The DMA accesses the memory directly, so will not see data pending in write buffers, or held in a write-back cache by the CPU. ARM designs don't waste transistors on complex bus-snooping (like Intel x86), you need to manage usage, and be cognizant of the hazards.

On the CM7 CPU you'll want to Flush (Clean) the cache before DMA writes, and Invalidate the cache after DMA reads.

You should use the SCB_CleanDCache_by_Addr() and SCB_InvalidateDCache_by_Addr() CMSIS functions which act on the 32-byte aligned address granularity used by the core. Watch for side-effects if your structures aren't suitably aligned in memory.

Or the F7 you might consider using the DTCM RAM as this isn't cached.

Perhaps pull the Programming Manual?

https://www.st.com/content/ccc/resource/technical/document/programming_manual/group0/78/47/33/dd/30/37/4c/66/DM00237416/files/DM00237416.pdf/jcr:content/translations/en.DM00237416.pdf

and some understanding of CPU architecture and caching concepts.

[waclawek.jan]

What exactly do you mean by inconsistencies? Can you please give examples, maybe a sketch if needed?

> Or any hardware logic to prevent the CPU from writing/reading to the memory, when the DMA is doing so?

In one clock cycle of the memory (which is usually equal to system clock cycle), only one bus master can access the memory. Access is read or write of one byte or halfword or word. Bus masters can access the memory interleaved, though.

In the 'F7, there are additional concerns if you use cached areas of memory for DMA; cache is part of the processor, thus DMA can't "see into" the cache and vice versa, processor if looks at cached memory area may see only the cache content and not the memory which might've been changed by DMA meantime.

JW