CONFUSION IN STM32F302R8 MASTER TRANSFER DATA DIAGRAM

[WM_IR]

Im having a confusion on my diagram about the EV2. Why does the EV2 happens during the transfer of data1? and it does not happen during transfer of data2? Or could someone explain about my master transfer diagram? the MCU model is STM32F302R8

[TDK]

Once data1 is sent to the shift register to be sent out on the line, the register is available and the TXIS event fires again. It's a hardware design decision. Doing it this way allows for some slack in timing in handling the EV2 event without slowing down the transfer. Note the clock stretch after the first ACK and before data1 can be sent out due to the delay in populating the register. If the hardware waited until the ACK, there would be less time to populate the register without causing another slowdown/clock stretch on the bus.

[WM_IR]

So, actually what does the EV1 and EV2 do? because it says there the EV2: TXIS ISR: wr data2

[TDK]

EV1 represents the statement within your I2C ISR handler when you’re handing the TXIS flag and you send data to the I2C TXDR data register.
Same for EV2, but with data2 instead of data1.

[WM_IR]

I try to visualize what is your answer. After few hours I found this figure in the ref manual. So basically, during the data1 transfer, the data2 is already inside the I2CTXDR register waiting to be sent out after data1 is sent. This will help in data transfer without any delay. Is that right?

[TDK]

More of less. Part way through shifting out data1 on the SDA line, data2 is written to TXDR.