CMOS- and TTL-compliant

[Lyu.1]

Hi,Master:

platform: STM32G070CB

Quesion:

Regarding CMOS - and TTL compliant, the manual provides the above diagram. How does it achieve compatibility? When Vin>min (07 x VDDIO, 2), is it considered that the input is at a high level? When Vin<min (0.3 x VDDIO, 0.8), is the input considered low?

Thank you very much!

[TDK]

> How does it achieve compatibility?

Above the gray region, the inputs are guaranteed to be read as high.

Below the gray region, the inputs are guaranteed to be read as low.

Because the requirements on CMOS/TTL (red and blue regions, plus/minus the region cut or added by the dashed line) have no overlap with the gray region, this chip satisfies CMOS/TTL requirements.

> When Vin>min (07 x VDDIO, 2), is it considered that the input is at a high level? When Vin<min (0.3 x VDDIO, 0.8), is the input considered low?

Yes

[Lyu.1]

Thanks. 

Is it also applicable for TT type pins (non-FT type)? For example, Vin > 0.8 but Vin < 0.3 x VDDIO are also considered low?

[Lyu.1]

I still have a question, as follows:

The table above describes: <0.3VDDIO is considered low, >0.7VDDIO is considered high.

So in the figure below, only the R region is high, and the G region should be an unknown level, right?

If right, The G-zone level is within the TTL input high requirement, but is not considered high. This is not a violation of "CMOS- and TTL-compliant".

[TDK · Accepted solution]

Refer to the "guaranteed by design" values in the datasheet, which correspond to regions outside of the gray zone in the picture. The G region is guaranteed by design to be logic high per this value in the datasheet.

[Lyu.1]

Ok, I see, thank you very much！