Can the L4R5 OCTOSPI interface be configured as a slave
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‎2019-09-11 8:37 AM
Hi,
Can the L4R5 OCTOSPI interface be configured as an SPI or Hyperbus slave so that it's flash memory can be accessed and addressed via SPI from a master device?
Is it possible to configure the L4R5 OCTOSPI so that the device appears as an external flash memory to an SPI master device?
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OctoSPI
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STM32L4 Series
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‎2019-09-11 9:14 AM
I would think to put this in the STM32 2020 wish list...
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‎2019-09-11 9:17 AM
The complexity of doing that seems to offer little in the way of rewards.
Perhaps you can make some dual-port mailbox memory with a CPLD/FPGA ?
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