Can't tune FMC SRAM MUX mode to stm32h745zit

[Kondratev.Georgiy]

Hi I am having a problem. I want to connect an external SRAM to stm32h745zit using registers 74hc573. But I can’t configure FMC correctly. The findings do not form the necessary signals. At the same time, the same circuit works both on F103Vxx and F407Vxx, which only have SRAM MUX mode. Help solve this problem.

[waclawek.jan]

So, what have you done, what is the expected and what is the observed behaviour?

JW

[Kondratev.Georgiy]

Hi, in CubeMX I configured FMC as PSRAM, set timings. Filled the firmware in m / k. Checked registers, bits set correctly. I connected the analyzer and did not see the correct signals. Firstly, NBL1 and NBL2 behave strangely, they immediately turn to a low level, although they must change their state alternately during RD / RW, the low byte NBL0, the high NBL1. The NEx signal is not formed on the M7 core. Or in H745 FMS works differently.

[Kondratev.Georgiy]

This is the best I have achieved on the M4 core. 0 - NE1, 1 - NL, 2 and 3 - NBL1 & NBL2, 4 - RD, 5 and 6 - address DA0, DA1.

[Kondratev.Georgiy]

hsram1.Instance = FMC_NORSRAM_DEVICE;
  hsram1.Extended = FMC_NORSRAM_EXTENDED_DEVICE;
  /* hsram1.Init */
  hsram1.Init.NSBank = FMC_NORSRAM_BANK1;
  hsram1.Init.DataAddressMux = FMC_DATA_ADDRESS_MUX_ENABLE;
  hsram1.Init.MemoryType = FMC_MEMORY_TYPE_PSRAM;
  hsram1.Init.MemoryDataWidth = FMC_NORSRAM_MEM_BUS_WIDTH_16;
  hsram1.Init.BurstAccessMode = FMC_BURST_ACCESS_MODE_DISABLE;
  hsram1.Init.WaitSignalPolarity = FMC_WAIT_SIGNAL_POLARITY_LOW;
  hsram1.Init.WaitSignalActive = FMC_WAIT_TIMING_BEFORE_WS;
  hsram1.Init.WriteOperation = FMC_WRITE_OPERATION_DISABLE;
  hsram1.Init.WaitSignal = FMC_WAIT_SIGNAL_DISABLE;
  hsram1.Init.ExtendedMode = FMC_EXTENDED_MODE_DISABLE;
  hsram1.Init.AsynchronousWait = FMC_ASYNCHRONOUS_WAIT_DISABLE;
  hsram1.Init.WriteBurst = FMC_WRITE_BURST_DISABLE;
  hsram1.Init.ContinuousClock = FMC_CONTINUOUS_CLOCK_SYNC_ONLY;
  hsram1.Init.WriteFifo = FMC_WRITE_FIFO_ENABLE;
  hsram1.Init.PageSize = FMC_PAGE_SIZE_NONE;
  /* Timing */
  Timing.AddressSetupTime = 5;
  Timing.AddressHoldTime = 3;
  Timing.DataSetupTime = 6;
  Timing.BusTurnAroundDuration = 5;
  Timing.CLKDivision = 16;
  Timing.DataLatency = 17;
  Timing.AccessMode = FMC_ACCESS_MODE_A;
  /* ExtTiming */
 
  if (HAL_SRAM_Init(&hsram1, &Timing, NULL) != HAL_OK)
  {
    Error_Handler( );
  }
 
  HAL_SetFMCMemorySwappingConfig(FMC_SWAPBMAP_SDRAM_SRAM);

[waclawek.jan]

I don't have personal experience with 'F7, but

> NBL1 and NBL2 behave strangely, they immediately turn to a low level, although they must change their state alternately during RD / RW, the low byte NBL0, the high NBL1

sounds like byte accesses were turned into word accesses. This is an optimization the processor may do when the accessed memory is not tagged as Device in the MPU. So try to look at that direction (and search on this forum).

> The NEx signal is not formed on the M7 core.

What do you mean by this, it stays high all the time? Is it correctly set in GPIO?

JW

[Kondratev.Georgiy]

It's about the H745 duo core m / k. NE1 on PC7 and on the M4 core work, while on M7 it remains in a high state. And it works only with swap norpsram and sdram. I am using SRAM 61vw51216-7us.

[Kondratev.Georgiy]

The LCD TFT peripheral control node is operational. All control signals are present. True only in swap mode

HAL_SetFMCMemorySwappingConfig(FMC_SWAPBMAP_SDRAM_SRAM);

on the M7 core.