caches in h7 series

[Srinath_03]

hi, I'm using stm32h745 dual core MCU, in this i want to know about the caches.

these I cache and D cache are default enable are it will enable from IOC configuration of M7 core.

if not enabled from IOC still these caches will work automatically?

due to these caches, I can't be able to run the spi with DMA mode, this cache made the dma to halt in dma handler itself.

so, my question is how to work with these with or without enabled cache. I tried of changing the dma buffer to a non-cacheable memory, but I couldn't I don't know why, the location change is also not happening correctly.

can someone help to solve this how to work with caches with DMA enabled, is there any video or source available for caches.

regards,

Srinath

[mƎALLEm · Accepted solution]

Hello,

1- To enable the cache you need to enable it yourself in your code or in CubeMx. It's disabled by default.

2- Using DMA you need to ensure the data coherency between CPU and DMA either my disabling the cache in the concerning memory region (used by CPU and DMA) using MPU, or using cache maintenance.

I suggest you to refer to this application note: AN4839 "Level 1 cache on STM32F7 Series and STM32H7 Series".

Refer to the section 3.2 Example for cache maintenance and data coherency as an example.

Hope that helps

[Srinath_03]

hi @mƎALLEm thanks for your response, i will look at it and i will ask for the doubts,

regards,

srinath

[mƎALLEm]

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@Srinath_03 wrote:

 i will look at it and i will ask for the doubts,

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 For further questions please open a new thread and close this one by accepting as solution my previous post.

Thank you.