Bug in STM32F103: enabling FSMC clock pulls up PB7

[owlm00n]

I have an STM32F103 board call 野火STM32F103ZE_霸道开发板，i found  enable  FSMC clock will pull up PB7  GPIO to 3.26v ,   i try decrease my code ceaselessly to verify this bug, finaly it can reproduce bug easily like this 

#include "stm32f10x.h"

int main (void)
{
//RCC->AHBENR |= 0x100//RCC_AHBPeriphClockCmd ( RCC_AHBPeriph_FSMC, ENABLE );
*( unsigned int * )0X40021014 |= ( (1) << 8);
}

void SystemInit(void)
{
// nothing in here
}

Is this a problem specific to a single chip or a more general chip?

[owlm00n]

Excellent answer, thanks

1-Now I know how it works,  it is diffcult to know without you answer, learn a lot.

so you can disable it by setting AFIO_MAPR2.FSMC_NADV (don't forget to enable AFIO clock in RCC before writing to its registers).

---

2-I try this way , but FSMC_NADV bit cat write to True, so PB7 always pullup when  FSMC clock Enable.

[waclawek.jan]

Do you have AFIO clock enabled in RCC?

JW

[owlm00n]

Sure.

Besides，I get it fron Chinese forum，I think it may be a true bug.

[waclawek.jan]

Interesting. I didn't know about this erratum.

It should apply only to STM32F103xC/D/E (see STM32F103xC/D/E errata) - as you said you have the 'F103ZE, that unfortunately applies there.

It appears that according to e.g. the larger STM32F103xF/xG errata, the problem has been fixed in those chips. I understand this won't help you with that particular board, sorry.

JW

[owlm00n]

I have checked my chip, it is STM32F103ZET6 same as the schematic, and checked it on the chip (forgot to post),

because I download the STM32F103xF/xG errata first.

[owlm00n]

No need to say sorry， I only realized this time that I should check the erratum rather of asking question.

Just like you see from nickname，Probably no one in my time zone is available to help at this hour.

Thank you for your expertise and passion.