Bug in STM32F103: enabling FSMC clock pulls up PB7

owlm00n · ‎2025-11-11

I have an STM32F103 board call 野火STM32F103ZE_霸道开发板，i found enable FSMC clock will pull up PB7 GPIO to 3.26v , i try decrease my code ceaselessly to verify this bug, finaly it can reproduce bug easily like this

#include "stm32f10x.h"

int main (void)
{
//RCC->AHBENR |= 0x100//RCC_AHBPeriphClockCmd ( RCC_AHBPeriph_FSMC, ENABLE );
*( unsigned int * )0X40021014 |= ( (1) << 8);
}

void SystemInit(void)
{
// nothing in here
}

Is this a problem specific to a single chip or a more general chip?

mƎALLEm · ‎2025-11-11

Hello @owlm00n and welcome to the ST community,

1- This statement is not clear: "野火STM32F103ZE_霸道开发板" even I translate it I got: "Wildfire STM32F103ZE_Dominator Development Board" could you please clarify?

2- First, ensure nothing is connected to the FSMC_CK, do you confirm that?

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Andrew Neil · ‎2025-11-11

@mƎALLEm wrote:
1- This statement is not clear: "野火STM32F103ZE_霸道开发板" even I translate it I got: "Wildfire STM32F103ZE_Dominator Development Board" could you please clarify?

From that translation, I found "Wildfire F103-Domineering-V1/V2 Stm32f103zet6 Development Board Learning Board Core Plate Arm Development Board":

https://www.aliexpress.com/i/1005008868422232.html

@owlm00n - is that the one?

This is why it's important to give a link - so that readers can be certain of what you're referring to!

Are you certain it is a genuine ST chip on the board?

A complex system that works is invariably found to have evolved from a simple system that worked.
A complex system designed from scratch never works and cannot be patched up to make it work.

owlm00n · ‎2025-11-11

Thank you for reply,

1- this is the product introduce of the "野火STM32F103ZE_霸道开发板" board ：
野火STM32F103ZE_霸道开发板 — 野火产品资料下载中心文档
and the Github page of project

Embedfire-stm32f103-badao

we can get Hardware schematic diagram in this path：

https://github.com/Embedfire-stm32f103-badao/ebf_stm32f103_badao_hardware/blob/master/hardware/F103_%E9%9C%B8%E9%81%93_V2/%E5%8E%9F%E7%90%86%E5%9B%BE/%E9%87%8E%E7%81%AB_F103%E9%9C%B8%E9%81%93_%E5%8E%9F%E7%90%86%E5%9B%BE_V2.0.pdf

2-It is my understanding that FSMC_CK is not a GPIO, I don't know which pin is corresponding to FSMC_CK.

mƎALLEm · ‎2025-11-11

@owlm00n wrote:

2-It is my understanding that FSMC_CK is not a GPIO, I don't know which pin is corresponding to FSMC_CK.

If you are not sure which pin is corresponding to FSMC_CK, how did you conclude the pin is pulled-up when you enable the FSMC clock in RCC?

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owlm00n · ‎2025-11-11

YES , the the board in picture is same as mine , i give the Github link above, hope it will hlep.

owlm00n · ‎2025-11-11

@mƎALLEm wrote:
@owlm00n wrote:
2-It is my understanding that FSMC_CK is not a GPIO, I don't know which pin is corresponding to FSMC_CK.
If you are not sure which pin is corresponding to FSMC_CK, how did you conclude the pin is pulled-up when you enable the FSMC clock in RCC?

My project need GB7 pin as pwm ,and use ILI9341 at the same time.

and i see the hardware schematic diagram , no FSMC pin is connect GB7.

mƎALLEm · ‎2025-11-11

@mƎALLEm wrote:

@owlm00n wrote:

2-It is my understanding that FSMC_CK is not a GPIO, I don't know which pin is corresponding to FSMC_CK.

If you are not sure which pin is corresponding to FSMC_CK, how did you conclude the pin is pulled-up when you enable the FSMC clock in RCC?

Ok May be I misunderstood your question here. You mean by "FSMC clock" the FSMC RCC clock enable, not the FSMC_CK pin.

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mƎALLEm · ‎2025-11-11

Unfortunately, all the links in Chinese. Need to browse the entire tree structure in github to find what we need to look at. The PDF you shared don't show all the hardware available on the board. I think there is an SRAM on the board based on the picture but I don't see it in the schematic.

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waclawek.jan · ‎2025-11-11

This is not a bug, it's how the 'F1 GPIO works.

The 'F1 family was the first STM32 family, and its GPIO is a very simplistic design (GPIO in all newer STM32 has a different, more coherent design): the individual modules (like TIM, I2C, SPI, etc.) output signals are simply OR-ed together. Some modules have individual enable bits for their outputs, e.g. in TIM (TIMx_CCER.CCxE), so you can enable the module but not enabling its output it won't influence other module's signal at the same pin; but many modules don't have such individual enables, and all their pins are enabled at once. This is also the case of FSMC, where, once you enable its clock in RCC, its signals start to "occupy" the pins where it is connected.

Pin PB7 is FSMC_NADV, which is used only in (relatively rare) multiplexed-bus designs. ST is aware of the fact that enabling FSMC would occupy PB7 even if you don't need FSMC_NADC signal, so you can disable it by setting AFIO_MAPR2.FSMC_NADV (don't forget to enable AFIO clock in RCC before writing to its registers).

JW