Any limits on flash selection for STM32N6

[Brenden_PLUS]

From my understanding all STM32N6 chips need a external flash chip and there's a static stage 0 boot loader. 

So if this is true is there any limitation's on the brands of flash or speed/address bit size limitations?

With the previous stage 0 bootloader for a different non ST product had a lot of limitation on the flash that could be used.

* 16 bit flash address only

* Only support a few brands of flash chips. 

[AScha.3]

1. Supported External Flash Memory Brands and Types

STM32 MCUs with Quad-SPI, Octo-SPI, Hexadeca-SPI (HSPI), and XSPI interfaces support a wide range of external flash memory brands and types. These interfaces are compatible with:

• Single-SPI, Dual-SPI, Quad-SPI, Octo-SPI, and 16-bit protocol memories
• HyperBus™ protocol memories (e.g., HyperRAM, HyperFlash)

Supported memory suppliers include Macronix, Adesto, Micron, AP Memory, Infineon, Winbond, and ISSI. Example supported parts:

• Quad-SPI: Micron MT25QL128A, NUMONIX N25Q256A, Macronix MX25L5124G, Infineon S25FS128SIFI000
• Octo-SPI: Macronix MX25UM51245G, MX25LMS51245G, Infineon S71KL512SC0BHI00
• XSPI: Macronix MX66UW1G45GXDI00, APmemory APS256XXN-OBR-BG

There are no explicit brand limitations, but compatibility should be verified with the STM32 datasheet and reference manual for your device.

[TDK]

@AScha.3 This question is specific to the STM32N6 which is unique in that it relies on external flash to boot up. I would not trust a generic AI answer to be accurate here.

[AScha.3]

@TDK  , your right, so lets see:

1. Address Bit Size and Memory Access Limitations

• When using the STM32N6 in Macronix OctaRAM™ mode (XSPI_DCR1 register MTYP[2:0] = 011), only 13 bits of row address are decoded and sent to the memory. This restricts access to 8 K of 1-Kbyte blocks (8 Mbytes). This limitation does not apply to PSRAMs or HyperRAM™ memories.
• For 256-Mbyte memories in memory-mapped mode, transactions that end at the last address may fail, causing incomplete writes or deadlocks on reads. It is recommended to avoid transactions that end at the last memory address.
• If DQS is enabled and a wrap includes the last memory address, data corruption or deadlock may occur. Such wraps should be avoided.

2. Supported Flash Memory Types, Interface Speeds, and Addressing

• STM32N6 supports external flash memory via Quad-SPI, Octo-SPI, Hexa-SPI, and XSPI interfaces.
• Maximum AHB/AXI frequency: 400 MHz.
• Maximum Octo-SPI and Hexa-SPI frequency: 200 MHz each.
• XSPI interface supports a wide range of external serial memories, including those from Macronix, APmemory, Infineon, Winbond, and ISSI, and supports protocols such as OCTABUS and HyperBus.
• For detailed address size and configuration, refer to the STM32N6 reference manuals and datasheets.

3. Brand and Model Limitations

• The STM32N6 boot ROM supports booting from various types of external memory, including sNOR x4/x8 flash, HyperFlash™, SD cards (SD V6.0), and eMMC (V5.1).
• There are no explicit restrictions on brands or models; compatibility is determined by supported interface types and electrical characteristics, not by manufacturer.

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Summary

There are no explicit limitations on the brands of external flash memory for STM32N6, as long as the memory is compatible with the supported interfaces (Quad-SPI, Octo-SPI, Hexa-SPI, XSPI) and meets the required electrical characteristics. However, there are technical limitations regarding address bit size and memory access, especially in certain modes and with large memory devices. Always consult the STM32N6 reference manual and datasheets for detailed configuration and compatibility.