Hi,
Im using STM32g0b1 ADC in continous mode.
I am continously converting channels 0,1 and 2. Everything works perfect when clocking the ADC with PCLK/2.
SYSCLOCK is 64MHz
PCLK is 64MHz
so ADCCLOCK is 32MHz.
I get End-of-Conversion Interrupts correctly and each 3rd EOC interrupt I am getting an End-of Sequence interrupt.
If I use PCLK/4 (ADCCLOCK 16MHz) the timing for conversions is seemingly as intended (everything takes exactly double time), however channels get mixed.
I found that End-of Sequence interrupt occurs every two conversion (instead of every three conversion) and I can no longer match Conversion results to channels.
In fact channel 2 conversion result ends up as first, second or third result within a series.
Remark: I started to check for End-of Sequence interrupt only after getting above problem.
Is there restriction about clocking the ADC?
