cancel
Showing results for 
Search instead for 
Did you mean: 

STM32N6 + ThreadX/FileX + SDMMC2: FX_IO_ERROR (144) during continuous video frame writes, display corruption observed

Aashritha_Vuda
Associate II

Hey Folks,

 

Description:

I am using STM32N6570-DK with Azure RTOS (ThreadX + FileX) to store camera frames on an SD card using SDMMC2.

Use case:

Capture camera frames (RGB565, 320×240) using DCMIPP

Display frames via LTDC

Continuously write frames to SD card using fx_file_write()

Issue:

Small file read/write (text file) works correctly.

When continuously writing video frames (~153 KB per frame), FileX fails after 2–3 frames.

FileX returns FX_IO_ERROR (144).

Failure occurs during media flush / directory update, not directly in application code.

 

Configuration:

From fx_stm32_sd_driver.h:

#define FX_STM32_SD_DMA_API                                   1
#define FX_STM32_SD_CACHE_MAINTENANCE          0
#define FX_STM32_SD_MAX_TRANSFER_SECTOR    16

#define FX_STM32_SD_DEFAULT_SECTOR_SIZE        512


FX_STM32_SD_WRITE_CPLT_NOTIFY() waits on a ThreadX semaphore.

SDMMC2 interrupt enabled.

GPDMA interrupts currently not enabled.

NVIC priority for SDMMC2 was initially 0

Additional Observations:

Indicates possible DMA/cache/interrupt contention between:

SDMMC2

Camera (DCMIPP)

LTDC

Questions:

For STM32N6 + FileX + SDMMC2, when FX_STM32_SD_DMA_API = 1:

Is GPDMA mandatory?

Which GPDMA IRQs must be enabled?

If SD driver uses polling or IT mode, should FileX still wait on a semaphore in
FX_STM32_SD_WRITE_CPLT_NOTIFY()?

Is there a recommended maximum sector count per SD write for STM32N6?

Are there recommended NVIC priorities for:

GPDMA

DCMIPP / LTDC
when using ThreadX + FileX?

Is there any reference design for high-throughput SD writes (video logging) on STM32N6?

NOTE: Any Assistance will be appreciable.....

Thankyou.

 

Best Regards,

Aashritha

 

 

 

 

 

0 REPLIES 0