STM32N6 + ThreadX/FileX + SDMMC2: FX_IO_ERROR (144) during continuous video frame writes, display corruption observed

[Aashritha_Vuda]

Hey Folks,

Description:

I am using STM32N6570-DK with Azure RTOS (ThreadX + FileX) to store camera frames on an SD card using SDMMC2.

Use case:

Capture camera frames (RGB565, 320×240) using DCMIPP

Display frames via LTDC

Continuously write frames to SD card using fx_file_write()

Issue:

Small file read/write (text file) works correctly.

When continuously writing video frames (~153 KB per frame), FileX fails after 2–3 frames.

FileX returns FX_IO_ERROR (144).

Failure occurs during media flush / directory update, not directly in application code.

Configuration:

From fx_stm32_sd_driver.h:

#define FX_STM32_SD_DMA_API                                   1
#define FX_STM32_SD_CACHE_MAINTENANCE          0
#define FX_STM32_SD_MAX_TRANSFER_SECTOR    16

#define FX_STM32_SD_DEFAULT_SECTOR_SIZE        512

FX_STM32_SD_WRITE_CPLT_NOTIFY() waits on a ThreadX semaphore.

SDMMC2 interrupt enabled.

GPDMA interrupts currently not enabled.

NVIC priority for SDMMC2 was initially 0

Additional Observations:

Indicates possible DMA/cache/interrupt contention between:

SDMMC2

Camera (DCMIPP)

LTDC

Questions:

For STM32N6 + FileX + SDMMC2, when FX_STM32_SD_DMA_API = 1:

Is GPDMA mandatory?

Which GPDMA IRQs must be enabled?

If SD driver uses polling or IT mode, should FileX still wait on a semaphore in
FX_STM32_SD_WRITE_CPLT_NOTIFY()?

Is there a recommended maximum sector count per SD write for STM32N6?

Are there recommended NVIC priorities for:

GPDMA

DCMIPP / LTDC
when using ThreadX + FileX?

Is there any reference design for high-throughput SD writes (video logging) on STM32N6?

NOTE: Any Assistance will be appreciable.....

Thankyou.

Best Regards,

Aashritha

[MFARH.1]

Hello  @Aashritha_Vuda ,

Is GPDMA mandatory when FX_STM32_SD_DMA_API = 1?
Not necessarily. The STM32N6 example uses HAL_SD_WriteBlocks_DMA() without enabling any GPDMA IRQ in the MSP, and completion is signalled via SDMMC2_IRQn. So on N6, the SD DMA mode can work through the SDMMC’s own DMA/IDMA mechanism (depending on the CubeMX configuration) with SDMMC2_IRQn only.

However, if your CubeMX configuration routes SDMMC2 through GPDMA channels, then yes: you must enable the IRQs for the corresponding GPDMA RX/TX channels; otherwise, the semaphore will never be given.

Which IRQs should be enabled?

• Minimum: SDMMC2_IRQn.
• If you use GPDMA: the GPDMA*_Channel*_IRQn assigned to SDMMC2 RX/TX plus SDMMC2_IRQn.

If the driver is in polling/IT mode, should FX_STM32_SD_WRITE_CPLT_NOTIFY() wait on a semaphore?

• DMA/IT mode: yes, that is expected.
• Pure polling mode: no, you should either not wait on a semaphore, or perform a polling-based wait, because no ISR callback will be triggered to release it.

Recommended maximum transfer size (number of sectors)
16 sectors (8 KB) is conservative. For sequential logging, 32 or 64 sectors can improve throughput, provided you do not hit timeouts and your buffers are DMA-safe (alignment + cache constraints). In practice, the main limitations come from:

1. Cache / MPU settings
2. Timeouts
3. Bus contention

Recommended NVIC priorities (SDMMC / DMA / DCMIPP / LTDC)
In the example, SDMMC2_IRQn is set to priority 5 (and SD_DETECT EXTI to 14). The practical guidelines are:

• Avoid priority 0 (too aggressive under an RTOS).
• Give SDMMC2/DMA a sufficiently high priority to avoid missing completions (which would lead to timeouts → FX_IO_ERROR), but not so high that it disrupts real-time camera/display processing.

A reasonable starting point is:

• SDMMC2_IRQn ≈ 5
• DCMIPP / LTDC at slightly lower priority (numerically > 5) if you want to favour reliable SD writes;
  or the opposite if you absolutely want zero dropped frames. In all cases, do not let SDMMC2 get “starved”.

Reference design for “high throughput video logging”
The ST example does not implement video streaming, but it demonstrates the correct building blocks for N6: DMA + semaphore + SDMMC2 IRQ + MPU (non-cacheable) / or proper cache maintenance.

GitHub reference:
STM32CubeN6/Projects/STM32N6570-DK/Applications/FileX/Fx_uSD_File_Edit at main · STMicroelectronics/STM32CubeN6

Regards,

Maher