Hi,
I am experiencing a core freeze issue on STM32H7S3L8 MCU, as described below.
UPDATE 1: Most probably Data Cache is the main culprit, closing Data Cache in bootloader solves the problem. Application code Enables Data Cache and we have never observed any freeze errors in application code. Relocating the HASH code changes the behaviour but same error observed for both HW and SW Hash functions so Hash is probably irrelevant! (see the comment section.)
In the bootloader, I compute a HASH over the application image stored in external XSPI flash (memory-mapped XIP). After this process, "we believe", the core occasionally freezes and becomes inaccessible through the debug probe.
In the first scenario bootloader firmware remains unchanged; only the application binary varies. The freeze depends on the application binary. Some application images consistently trigger the issue on every power cycle, while others run without problems.
In the second scenario when using an application image that triggers the freeze and modifying the bootloader, disabling Data Cache or either by relocating the HASH processing block (see. “HASH HW START” and “HASH HW END”) or by commenting out a single line such as // HAL_HASH_DeInit(&hash); or // __HAL_RCC_HASH_CLK_DISABLE(); prevents the freeze and allows a normal jump to the application.
My observations:
1. Error doesn't happen when Data Cache is disabled.
2. Relocating the HASH HW code changes the behaviour
3. Changing the input clock source has no effect on the behaviour (HSE <-> HSI), core freezes with the exact same app binary.
4. I could not trigger the problem using a software HASH implementation.
Given the nondeterministic behavior, I was unable to reach a solution.
I welcome any advice or questions. Thanks in advance.
Pseudo-code which exhibits the exact flow of my bootloader. (I can't share the bootloader itself, unfortunately)
Systick_Init();
// Region 0: Start Addr: 0, SIZE_4GB, NO_ACCESS, SubRegDisable: 0x87
// Region 1: Start Addr: 0x9000000, SIZE_32MB, FULL_ACCESS, SubRegDisable: 0x00, NOT_SHAREABLE, INSTRUCTION_ACCESS_ENABLE
MPU_Init();
SCB_EnableICache();
SCB_EnableDCache();
NVIC_SetPriorityGrouping(NVIC_PRIORITYGROUP_4);
Clock_Init(); // Error occurs working with HSE and also with HSI mode.
CRC_Init();
LL_PWR_ConfigSupply(LL_PWR_DIRECT_SMPS_SUPPLY);
OptionBytes_Program(); // XSPI works in HSLV Mode
// XSPI1 and XSPI2 uses corresponding MCEs
XSPI1_Init(); // Uses ST EXTMEM Library for External FLash
MCE1_Init();
XSPI2_Init(); // Used for external PSRAM
MCE2_Init();
// HASH HW Start
// Core freezes somewhere after this point, beware that XSPI1 is in memory mapped mode // and we pass external flash address directly to the HAL_HASH_Start();
HASH_Init(); // Poll mode, SHA256 algo, HASH_BYTE_SWAP
// XSPI_APP_FLASH_BASE = 0x90000512, XSPI_APP_FLASH_SIZE = 512kB-512byte
uint8_t digest[32];
HAL_HASH_Start(&hash, XSPI_APP_FLASH_BASE, XSPI_APP_FLASH_SIZE, digest, 2000);
HAL_HASH_DeInit(&hash);
__HAL_RCC_HASH_CLK_DISABLE();
// HASH HW END
signature_success = uECC_verify(public_key, digest, signature);
