2024-02-09 01:05 PM
Hi everyone, I’m using H747 eval board and I’ve configured Adc1 and adc2 (on M4) to acquire 3 signals each.
I’m using DMA but I can’t read correct values in the buffer..how is it composed? Which is the sequence of channels in the DMa buffer if I have, for example, Channel 0-1-2 on adc1 and channel 3-5-6 on adc2 active?
Thanks :smiling_face_with_smiling_eyes:
2024-02-09 01:28 PM
It can vary based on settings, but in the typical and most common configuration, the buffer will alternate between uint16_t values for master and slave, so in this instance it would be channels 0, 3, 1, 5, 2, 6.
2024-02-11 01:08 AM
Thanks TDK,
so, because I have configured adc1 and adc2 in dual mode, I have just one 32-bit buffer which contains in the highest 16-bit the information about adc2 and in the lowest 16-bit the information about adc1.
If I have correctly understood, you mean that, in the first data of the buffer I have the sample of channel 0 adc1 and channel 3 adc2; in the second one channel 1 adc1 and channel 5 adc2 and so on..correct?
Some other questions:
- in Stm32Cube, is it correct that I have enabled DMA request for adc2 (in DMA settings)? I thought that I shouldn't configure it, because it was already configured in adc1, but if I remove this, I have a error.
- here is my configuration, can you check it please and tell me if it's correct?
- can you explain me please what does the parameter "delay between 2 sampling phases" refer to? How can I calculate this parameter? (And, the same for "Sampling time" in every Rank)
Thank you