STM32H503 SVD / RM ADC_CFGR_EXTSEL logical error?

[hijax_pl]

ADC_CFGR register and EXTSEL field.

In SVD this single field is split among four 1-bit long ones (according to RM0492) and enumerated values desciptions are messed up (adc_ext_trg0 & adc_ext_trg1 repeated for all 4 "subfields")

RM0492 discusses this as single field, which is correct, i.e.

"Bits 9:5 EXTSEL[4:0]: External trigger selection for regular group

These bits select the external event used to trigger the start of conversion of a regular group:
00000: adc_ext_trg0
00001: adc_ext_trg1
00010: adc_ext_trg2
00011: adc_ext_trg3
00100: adc_ext_trg4
00101: adc_ext_trg5
00110: adc_ext_trg6
00111: adc_ext_trg7
...
11111: adc_ext_trg31"

etc...

In the same time ADC_JSQR_JEXTSEL is defined as single 5-bit long field.

Bits 6:2 JEXTSEL[4:0]: External Trigger Selection for injected group

Logical inconsistecy...

Is SVD created from RM or vice versa?

Either way I think RM0492 (page 579), SVD and stm32h503xx.h files shall be corrected, to have both descriptions, i.e. EXTSEL & JEXTSEL aligned.

[Imen.D]

Hello @hijax_pl,

Thank you again for having reported the point related to SVD issue.

I escalated this request internally for fix within the internal ticket number: 197196 (this tracking number is only for reference, not available outside of ST).