STM32CubeMX linker scripts for F767ZI appear to use AXIM interface, but is that true?

[riwe]

The linkerscripts generated by the STM32CubeMX for STM32F767ZI appear to use the AXIM interface:

/* Specify the memory areas */
MEMORY
{
FLASH (rx) : ORIGIN = 0x08000000, LENGTH = 2048K
RAM (xrw) : ORIGIN = 0x20000000, LENGTH = 512K
}

But the default boot vector is set to address 0x0020 0000 which is a ITCM address:

# gdb console
> monitor stm32f7x options_read 0
stm32f2x user_options 0xFFC, boot_add0 0x0080, boot_add1 0x0040

boot_add0 0x0080 indicates ITCM.

When I move the boot vector by 128K, I have to set boot_add0 to 0x0088 (8*16K=128K) and set FLASH  ORIGIN in above linker script to 0x08020000. Otherwise it will not work. That is a bit confusing.

1. Is the MCU really booting from ITCM?
2. The binary code is not explicitly position-independent. I contains absolute jumps to addresses in the AXIM space because that is what LMA and VMA are configured to in the default linker scripts. Does my application only work by accident?
3. Should LMA and VMA in the linker script be separated, i.e. VMA of code sections points to the ITCM address space whereas LMA points to the AXIM address space so that OpenOCD can load the program?

Thanks.

[Pavel A.]

This works because the vectors are read as data. Assume your vectors table is located at 0x08000000 in the linker script, which is aliased to 0x00200000 (via TCM). Your reset address (via AXIM) at 0x08000004 is 0x08001235. 

When the MCU starts, it reads the start address from 0x00200004 and the value is 0x08001235. Then the program just runs using the AXIM addresses. Position-independent code is not needed.

The difference between TCM and AXIM access is illustrated on figure 3 in RM0410. The TCM path goes thru the ST proprietary ART instruction cache, while AXIM path bypasses ART. If you want instruction caching with AXIM, use the standard instruction cache of Cortex-M7.

[riwe]

Thanks. Indeed. When I set boot_add0 to 0x2000, then my program starts as well. So I was running via AXIM all the time. Now I wonder why STM uses AXIM in its generated linker scripts and never ITCM? The latter is desribed as faster and less complex than AXIM and instruction cache.