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I2C Communication issue on stm32H743zi Nucleo board

Gopika
Visitor

 

When using the STM32H743ZI Nucleo board as the I²C master and two STM32 Blue Pill boards as I²C slaves with different addresses, the master requests data from the slaves and the slaves respond accordingly. However, I²C communication  is unreliable during initial startup, and intermittent I²C errors are observed during runtime.

Is there anyone to help me with this issue.

Thank you.

2 REPLIES 2
Andrew Neil
Super User

Welcome to the forum.

Please see How to write your question to maximize your chances to find a solution for best results.

 


@Gopika wrote:

Is there anyone to help me with this issue.


What testing/investigation/debugging have you done so far?

What have you found?

Have you looked at the I2C lines with an oscilloscope?

If they're noisy or have other "analogue" issues (including inappropriate pullup value), then it's bound to be unreliable ...

Have you looked at the I2C lines with an analyser?

Have you instrumented your code and/or used the debugger to see what's happening inside the microcontrollers?

Have you tested your Master code with some known-good slaves?

 

Note that Blue Pills are not ST products, and likely do not contain genuine STM32s.

A complex system that works is invariably found to have evolved from a simple system that worked.
A complex system designed from scratch never works and cannot be patched up to make it work.
  • I have tried the 9 clock pulse generation method recommended in multiple ST community forum threads to recover the I2C bus when it gets stuck. Unfortunately, this method did not resolve the issue in my case.
  • During initial startup of the system i2c communication will not work.If I power OFF both boards, then power them ON again, and only perform a software reset on the master board, the I2C communication starts working correctly.Runtime missing also will be there(approximately after 1 hour of system reset).
  • The master I2C is configured to use DMA mode.
  • I do not currently have access to a logic analyzer, so I have not captured protocol-level traces.
  • The same slave device works reliably once the master and slave is reset, indicating the slave itself is likely not at fault.