Conflict in ITCM DTCM RAM while using ETHERNET and QUADSPI in memory mapped mode?

[rudolf.pribis]

I use STM32F769I-DISC1.

My program is based on LwIP_HTTP_Server_Socket_RTOS and QSPI_ExecuteInPlace (and https://github.com/vlcekji2/External-Loaders).

Basically, in external FLASH I have a program which handles a TCP server.

When using data and instruction cache, after a while, my program crashes in HardFault_handler.

Is there a conflict with using ITCM and DTCM RAM between QUADSPI in memory mapped mode and Ethernet?

When D & I caches are disabled, program runs.

I use MPU as Ethernet example suggests:

/* Configure the MPU as Normal Non Cacheable for Ethernet Buffers in the SRAM2 */
  MPU_InitStruct.Enable = MPU_REGION_ENABLE;
  MPU_InitStruct.BaseAddress = 0x2007C000;
  MPU_InitStruct.Size = MPU_REGION_SIZE_16KB;
  MPU_InitStruct.AccessPermission = MPU_REGION_FULL_ACCESS;
  MPU_InitStruct.IsBufferable = MPU_ACCESS_NOT_BUFFERABLE;
  MPU_InitStruct.IsCacheable = MPU_ACCESS_NOT_CACHEABLE;
  MPU_InitStruct.IsShareable = MPU_ACCESS_SHAREABLE;
  MPU_InitStruct.Number = MPU_REGION_NUMBER0;
  MPU_InitStruct.TypeExtField = MPU_TEX_LEVEL1;
  MPU_InitStruct.SubRegionDisable = 0x00;
  MPU_InitStruct.DisableExec = MPU_INSTRUCTION_ACCESS_ENABLE;
 
  HAL_MPU_ConfigRegion(&MPU_InitStruct);
 
  /* Configure the MPU as Device for Ethernet Descriptors in the SRAM2 */
  MPU_InitStruct.Enable = MPU_REGION_ENABLE;
  MPU_InitStruct.BaseAddress = 0x2007C000;
  MPU_InitStruct.Size = MPU_REGION_SIZE_256B;
  MPU_InitStruct.AccessPermission = MPU_REGION_FULL_ACCESS;
  MPU_InitStruct.IsBufferable = MPU_ACCESS_BUFFERABLE;
  MPU_InitStruct.IsCacheable = MPU_ACCESS_NOT_CACHEABLE;
  MPU_InitStruct.IsShareable = MPU_ACCESS_SHAREABLE;
  MPU_InitStruct.Number = MPU_REGION_NUMBER1;
  MPU_InitStruct.TypeExtField = MPU_TEX_LEVEL0;
  MPU_InitStruct.SubRegionDisable = 0x00;
  MPU_InitStruct.DisableExec = MPU_INSTRUCTION_ACCESS_ENABLE;
 
  HAL_MPU_ConfigRegion(&MPU_InitStruct);
 
  /* Enable the MPU */
  HAL_MPU_Enable(MPU_PRIVILEGED_DEFAULT);

[Tesla DeLorean]

As far as I'm aware the TCM memories are not cached.

For hard faults related to coherency issues with either cache or write buffers​, look very critically at use of InvalidateDCache type operations which are indiscriminate, unaligned, or exceed scope.

For things you believe are errata, you will need to engage more directly with ST support staff assigned to your account, and provide them with HW/SW illustrative of the failure mode. Pointing at a general repository probably won't suffice. ​