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STM32U083RCT6 drive level on 32.768kHz LSE

racc
Associate

‎2025-10-19 3:47 PM - last edited on ‎2025-10-21 2:55 AM by

Good day. I am working on a 32-pin STM32U083KCU6. This requires the use of LSE 32.768kHz crystal. I referred to AN2867 as the oscillator design guideline.

The LSE has the following specs:

  • Shunt capacitance - 1.15pF,
  • ESR - 70k,
  • Load capacitance - 7pF.
  • Calculated crystal gm is less than the STM32 Gmcrit so I think this crystal is ok to use.

My concern is the determination of Rext value as the measurement of the current through the crystal is not an easy measurement. To set baseline in the Rext value, I used the evaluation board NUCLEO-U083RC as reference since it uses a similar STM32U083RCT6. Looking at the evaluation board schematics, I see that the Rext R34 and R35 are both set to 0R. The LSE used in the evaluation board is NX2012SA-32.768KHZ-EXS00A-MU00527 which has a max level drive of 0.5uW. May I ask to what drive level is the MCU set to drive the crystal in the evaluation board? What is the power level the MCU drives the crystal considering the max level of drive of the LSE is 0.5uW? Appreciate your support on this topic. Thank you.

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4 REPLIES 4
mƎALLEm
ST Employee

‎2025-10-20 1:48 AM - edited ‎2025-10-20 1:49 AM

Hello @racc and welcome to the community

Please refer to this thread: Calculating Rext after increasing LSE Drive Level on STM32H7

The solution mentions that you don't need the Rext and it's not recommended for all of LSE oscillator on all STM32.

To give better visibility on the answered topics, please click on "Accept as Solution" on the reply which solved your issue or answered your question.
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racc
Associate
In response to mƎALLEm

‎2025-10-21 2:14 AM

Hi @mƎALLEm thank you for replying to my question.  I've actually seen this thread, but I would like to get more details/ data.  Are you able to answer these questions:

Does ST guarantee in the production level that the power level the crystal is driven to always less than 0.5uW?
Does ST have measurements in the evaluation board to prove this statement?

 

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Uwe Bonnes
Principal III
In response to racc

‎2025-10-21 2:26 AM

Drive levels are not specified in chapter 6.3 of the datasheet. So as there is no maximum drive level listed, there is no guarantee.

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mƎALLEm
ST Employee
In response to racc

‎2025-10-21 2:49 AM

This is the Gain margin provided in the datasheet:

mALLEm_0-1761039558628.png

Maximums specified by design, not tested in production. 

You need to select the correct drive level based on the crystal characteristics. Please read How to select a compatible crystal and load capacitors for STM32 with layout guidelines / Section  2. Calculation to validate the crystal compatibility with STM32

So for each drive level you need to do the same calculation until you find the correct drive level suitable for the crystal.

For the NUCLEO-U083RC board / NX2012SA-32.768KHZ-EXS00A-MU00527, I let the board's designers answer that question.

To give better visibility on the answered topics, please click on "Accept as Solution" on the reply which solved your issue or answered your question.
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