SRAM Clock Frequency for STM32N657X0H3Q (Nucleo-N657X0-Q)

[A_sharma]

Hi ST team,

I'm working with the Nucleo-N657X0-Q board (STM32N657X0H3Q MCU) and running the nx_iperf example from NetX Duo. I’d like to understand what the SRAM clock frequency is during this example's execution. In the release notes, it’s mentioned that the core clock is set to 600 MHz, although the maximum supported core clock is 800 MHz. I’m trying to determine:

• What is the default clock source and frequency for the SRAM in this MCU?
• Is the SRAM clock configurable separately from the system clock?

Any guidance or documentation references would be greatly appreciated.

Thankyou, 

A. Sharma

[STackPointer64]

Hello @A_sharma, and welcome to ST Community!

The SRAM is typically connected to the AXI bus or AHB bus so by default, the SRAM is clocked by the HCLK, which is usually set equal to the SYSCLK unless divided.

Best regards,