2025-12-13 10:05 AM
Hello everyone,
I am currently working on an audio project using the Nucleo-WB55 board and the SGTL5000 codec. I am using the SAI peripheral in I2S mode to transmit and receive audio data, but I am facing an issue when testing a simple loopback setup.
Nucleo-WB55
SGTL5000 audio codec (not yet fully connected — initial tests are loopback)
SAI SD line of Block A connected directly to SD line of Block B for loopback testing
SAI Block A: Master, Transmit
SAI Block B: Synchronous Slave, Receive
I2S standard, 16-bit data
TX and RX audio buffers: 16-bit elements, each with 10 entries
DMA enabled for both TX and RX
Interrupts enabled
Circular DMA mode used on SAI Block B (receiver)
Start SAI B reception with circular DMA.
Start a blocking transmission on SAI A:
HAL_SAI_Transmit(hsai_BlockA, buffer, sizeof(buffer), 1000);TX SD line is physically looped back to RX SD line.
In the RX buffer, only the first half of the data matches the transmitted data.
The second half always contains the same pattern of “garbage” values, not random but incorrect and consistent.
This happens every time under the same configuration.
I’m not fully clear on when the SAI master clock (MCLK) is active:
Is MCLK always active after HAL_SAI_Init()?
Or does it only become active when a transmission/reception starts?
Does DMA mode affect this in any way?
I would appreciate guidance or test ideas to:
Validate whether my SAI configuration is correct
Verify whether the issue is related to clocking, DMA alignment, buffer size, or frame configuration
Rule out synchronization issues between SAI A and B
Any suggestions on:
How to properly test SAI I2S loopback
What configurations are commonly overlooked
How to confirm that SAI clocks and frame sync are correct
How to correctly align DMA buffer sizes with SAI frame settings
would be extremely helpful.
If any additional information (CubeMX settings, code snippets, register values, schematics, etc.) would help, please let me know and I will provide it.
Thank you.
Umair Jarullah