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# what is inductance(uH) of the X-NUCLEO-NFC04A1

Associate II

There is a Spiral antenna in the X-NUCLEO-NFC04A1. The link is https://www.st.com/content/st_com/en/products/ecosystems/stm32-open-development-environment/stm32-nucleo-expansion-boards/stm32-ode-connect-hw/x-nucleo-nfc04a1.html

By the document AN2972(How to design an antenna for dynamic NFC tags),In section 3.2 Inductance of a spiral antenna

,there is a calculation formula about a spiral antenna.As follow,

those parameters are:

d = 40mm

N = 8

c = 35um

The result of inductance is   1.7870e-05H.

It is not 4.5uH,Why? because capacitance of st25dv04 is 28.5 pf.

For the ST25dv series,what is the best inductance of antenna? 4.5uH or not?

BR,

Liu

1 ACCEPTED SOLUTION

Accepted Solutions
ST Employee

​Hello Liu,

nothing particular to say about spiral parameters, they sound good to me.

concerning the schematic: you can remove C8 and C7 (they could be used to improve EMI robustness but are useless in your case. For same reason you can remove R10. It will simplify layout. Outer via of coil routing can be simplified too.

You'll find a quick and dirty illustration, just as an example, of these recommendation in the picture here attached.

Some additional optimization of the SCL, SDA , GP0 pull up resistors and C9 decoupling cap placement may be possible.

BR,

HC.

10 REPLIES 10
ST Employee

​Hello Liu,

you are right, there is an error in the document and a misleading information in the description:

the right formula is:

L=31.33.µ0. N².a²/(8a+11c) where:

• a is the mean radius of the spiral a=(ri+ro)/2 where ri is the inner radius and ro is the outer radius of the coil
•  and c = ro-ri, representing the width of the space occupied by the turns or the summ of turns width and turns spacing . In some literature dealing with stacked windings, it is called the thickness of wires, so sorry for the confusion)

with new formula and a=22mm and c=10mm, it comes L= 4.26µH which is more in line with what is expected.

Please keep in mind that this formula only estimates the self inductance of the coil and not the stray capacitance. Because of the self resonnance frequency caused by the presence of this stray capacitor (few pF generally), the actual  imaginary part of coil impedance is higher than 4.26µH*2*pi*13.56MHz. Finally coil impedance imaginary part is close to 4.7µH which is the chip impedance complex (28.5pF) close to 13.56MHz.

best regards,

HC.

Associate II

Thank you for your reply,Your method is right,but I want to design a double layer antenna（in PCB）.In the file your double layer antenna is coming soon, I don't know how it is going.I hope that you can give some design methods.What should I pay attention to?

BR,

LIU​

ST Employee

​Hello Liu,

let's consider two equal spiral inductances connected in series, stacked and perfectly coupled. Considering that they are perfectly magnetically coupled, (coupling factor k=1), a simple calculation leads to a total inductance Ltot=4.L where L is the inductance of a single coil.

In real life,  k never goes up to 1 with the result that a 2 layer coil never reaches 4.L; it does not really matter because the stray capacitance of each spiral and between layers will increase the imaginary part of coil impedance. An additional tuning cap footprint can be anticipated on the layout to adjust the tag tuning frequency.  So first define the total inductance L you need, calculate a signle layer spiral with Lsingle= L/4, layout your two layer antenna using the calculated spiral reported twice and use an additional tuning cap to trimm the tuning frequency on board.

If you use more than 2 layers, place the spirals on top and bottom, you'll get access to them in case a pcb quick fix is necessary. Follow PCB implementation recommendations in sections 3.5 of AN2972 (be sure not to have any copper area stoppering the magnetic field inside the coil, remove as much as possible copper around the antenna and don't put the antenna in an opened surface surrounded by copper).

Last recommendation: rotation orientation of turns shall remain the same on the two layers: for instance, seen from top, if top layer spiral turns clockwise from outside to center, a via shall be used to go to bottom layer, and bottom layer spiral shall start from this inner via and turn to outside clockwise too. Currents on all layers will then turn in the same rotation oientation. Else, magnetic flux in both spirals will be in opposite phase, cancel each other, and antenna won't work.

best regards,

HC.

Associate II

a = 14mm; N = 11; c = 8.6mm; u0; ri = 9.7mm; ro = 18.3mm.

Conductor: width = 0.6mm; spacing = 0.2mm; thickness = 35um.:*

BR

KIU​

Associate II

a = 14mm; N = 11; c = 8.6mm; u0; ri = 9.7mm; ro = 18.3mm.

Conductor: width = 0.6mm; spacing = 0.2mm; thickness = 35um.:*

BR

KIU

ST Employee

​Hello Liu,

nothing particular to say about spiral parameters, they sound good to me.

concerning the schematic: you can remove C8 and C7 (they could be used to improve EMI robustness but are useless in your case. For same reason you can remove R10. It will simplify layout. Outer via of coil routing can be simplified too.

You'll find a quick and dirty illustration, just as an example, of these recommendation in the picture here attached.

Some additional optimization of the SCL, SDA , GP0 pull up resistors and C9 decoupling cap placement may be possible.

BR,

HC.

ST Employee

​Hello Liu,

some connections are laking in you original design between spiral and ST25DV coil pads AC0/AC1 (I did not fix it in layout example above).

BR

HC.

Associate II

Hi HC，

Today I modify antenna parameter. As follow Figs, It shows how to test ro and ri value. Is it right?

By this way, ro = 18.9 mm, ri = 11.3 mm, N =10, ==> L = 4.4uH.As follow

By those spiral parameter, the PCB file is attached. Pls help me check again.

Thank you very much!

Thank you very much!

BR,

Liu

ST Employee

​Hello Liu,

Antenna is OK for me.

Concerning the Layout/schematic: maybe my comments are not relevant if your project is still under development but you do not use LPD pin:

• GPO pin is connected to Vcc thru a pull-up resitor while it is a  CMOS output ->  no need for pull up resitor contrary to 8-pin version of ST25DV-I²C where GPO is open-drain.
• I note also that GPO is not connected to any PCB IO.
• Why not switch to 8-pin version of the ST25DV-I²C?

best regards,

HC.