I am finding it difficult to get clear direction on best practices for how to do the layout for CSI and CSO. App note AN4985 says that "parasitic capacitance to ground should be made as small as possible", and then recommends using a coupling capacitor up to 2.7pF (C_COUP, between the 2 electrodes, I think... not sure). But, on the other hand, the reference design (Discovery Kit ST25R3911B-DISCO) has no C_COUP shown in the schematic -- maybe because there is enough capacitance already between the electrodes? -- and it has an RC of 1k and 12pF on both CSI and CSO, without explanation. It is not clear why we want to minimize parasitic capacitance to ground, but then we deliberately add 12pF of capacitance to GND. Some clarity on the design goals for CSI and SCO would really be appreciated. thanks!
