LD1117 Input & Output Capacitor requirements

[Matsuura]

I am currently designing a circuit using the LD1117S50CTR.
In the recommended circuit in the datasheet, Cin = 100 nF and Cout = 10 µF are specified.

For an LDO, I believe Cout is critical, while Cin is not as important.
Therefore, I am considering using 10 µF ceramic capacitors for both Cin and Cout.

Is there any issue with using a Cin value larger than the recommended 100 nF?

[RobK1]

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@Matsuura wrote:

For an LDO, I believe Cout is critical [...]

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Yes, this is very much the case, and the reason why you should be very careful choosing a ceramic capacitor. High K ceramics exhibit a very large voltage coefficient. So your 10µF capacitor might only be 4µF at 5V.

In the datasheet, there are numerous schematics where Cin is 10µF, so no problems there. 

[Peter BENSCH]

The LD1117 is a so-called quasi-LDO and dates back to a time when ceramic capacitors were rarely used and tantalum capacitors were the norm.

Input capacitor

Although a 100 nF capacitor is specified in the data sheet, you can use any capacitance value for this capacitor.

Output capacitor

For stability reasons, at least 10µF should be used here, and at least 22µF for the ADJ variants.
Please note: do not use a ceramic capacitor directly, but with a series resistor between 0.5-10 ohms. Reason: most linear regulators developed in the last millennium require output capacitors with a minimum ESR (electrolytic and tantalum capacitors have this inherently), which is practically non-existent in ceramic capacitors and therefore has to be simulated with a discrete resistor.

Hope that answers your questions and helps?

Regards
/Peter

[RobK1]

@Peter BENSCH 

I was under the impression that the minimum ESR requirements were specifically for (most) PNP-based LDO's? 

[Peter BENSCH]

In fact, the LD1117 is also partly based on this technology and is using a pnp and npn, which is why it is also called a quasi-LDO:

[Matsuura]

Thank you for your response.
I will proceed with using a 10 µF ceramic capacitor for the input capacitor.
However, I would like you to provide a circuit example showing how to use a 0.5–10 Ω series resistor with the output capacitor.
In addition, I already have a 10 µF electrolytic capacitor placed close to the output capacitor.
In this case, is the series resistor still necessary?

[Peter BENSCH]

For a high-frequency pulse, i.e. when considering the ESR, the (ideal) capacitors can be regarded as a short circuit. In this case, the relatively high-impedance ESR of C15 and the significantly lower ESR of C17 are in parallel. The resulting ESR is therefore even lower than that of C17. However, since the (total) ESR should be within the specified range, a resistor must be connected in series with C17.

Incidentally, you can omit C18, as C16 already has sufficient capacity. However, C18 can be useful if the supply line from C16 to C18 is very long.

Regards
/Peter