Application circuit

[Matsuura]

I am currently designing a circuit using the LD1117S50CTR.
In the recommended circuit in the datasheet, Cin = 100 nF and Cout = 10 µF are specified.

For an LDO, I believe Cout is critical, while Cin is not as important.
Therefore, I am considering using 10 µF ceramic capacitors for both Cin and Cout.

Is there any issue with using a Cin value larger than the recommended 100 nF?

[RobK1]

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@Matsuura wrote:

For an LDO, I believe Cout is critical [...]

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Yes, this is very much the case, and the reason why you should be very careful choosing a ceramic capacitor. High K ceramics exhibit a very large voltage coefficient. So your 10µF capacitor might only be 4µF at 5V.

In the datasheet, there are numerous schematics where Cin is 10µF, so no problems there.