STM32H747XIH6 DAC Issue

[Samudra]

We used a DAC with a sample-and-hold circuit on one of our custom boards. The RC filter was not mounted; instead, the DAC output was directly connected to an SMA connector. We enabled the DAC in the firmware, and after testing, we observed a large amount of current flowing through the STM32 board. Upon inspection, we found a short between the 3.3V rail and ground on the STM32 board.

Please find the attachment for your reference.

[mƎALLEm]

Hello,

which DAC instance?

R132 (0 ohm) fitted? (Short circuit on DAC1 output).

[Samudra]

Hai Sir,

DAC1_OUT1 is used. R132 is not mounted on the PCB, and the capacitor is also not mounted.

Still, we observed a short on 3V3. Can I mount R132 with a 5k resistor since it is connected to ground?

Please confirm.

Best regards,

Samudralankaiah.

[mƎALLEm]

Based on what you are saying now I don’t think the issue is coming from DAC1_OUT but from another stuff that I couldn’t determine based on the information you’ve provided at this stage.

[Samudra]

Hi Sir,

We are using the STM32 internal 12-bit DAC in buffered mode, as shown in the attached reference figure (Buffered / Non-Buffered DAC from the STM32 reference manual).

In our design, the DAC output (DAC_OUTx) is connected to an external circuit that behaves similar to a sample-and-hold load, where both resistive and capacitive components are present at the DAC output.

As per the reference diagram:

• RL represents the external load resistance.

• CL represents the load capacitance (sampling capacitor + PCB parasitics).

We plan to populate both RL and CL at the DAC output:

• RL to limit output current and improve stability.

• CL to model the sampling capacitor of the sample-and-hold circuit and to help reduce output noise.

Could you please confirm:

1. Whether mounting both RL and CL at DAC_OUTx is the recommended approach for sample-and-hold type loads when using the DAC in buffered mode.

2. Any recommended value ranges or stability considerations for RL and CL to ensure proper DAC settling time and output accuracy.

3. Whether additional external buffering is required for this configuration.

Your guidance will help us validate our DAC output stage design.

Thank you for your support.

Best Regards,
Samudralankaiah J