Problems Writing to SDRAM When Sharing FMC Data Lines with 8080 Interface

[joezzaghari]

Hello,
We are working with an STM32F429ZIT6TR to design an 800x480 LCD Display Controller Board,
I configured the FMC with the 8080 interface to receive data from Main Board (another provider), and also enabled SDRAM through the FMC. The LTDC is used to drive the LCD.

The plan is to transfer data to our Display Controller board via the 8080 interface and then use the LTDC for display refresh. The data lines are shared between the 8080 interface and the SDRAM, but they have different chip select signals.

we built a first prototype, but when we tried to write data into the SDRAM, we observed sporadic/incorrect values.

My questions are:

1. Could sharing the data lines between the 8080 interface and SDRAM cause signal integrity or bus contention issues, even though the chip selects are different?
2. Do you have any recommendations for PCB layout in this case?

[mƎALLEm]

Hello,

As you said it's managed by different chip select signals. The chips select is enabled by device at a time. 

Did you monitor the chip selects using an oscilloscope or a logic analyzer?

[joezzaghari]

Thanks for the reply, based on this I have questions on how to handle this chip selection.

To make it clear we have the following prototype

1.  LTDC+SDRAM for the RGB Display (800x480) where FMC configures SDRAM and provides sync and access to LTDC , Works fine (Where SDRAM uses FMC_A0 to FMC_A11 and FMC_D0 to FMC_D15)

2. On top of Point.1, additionally configure FMC as LCD_Interface(8080 Parallel) but just to read Parallel data from another controller. (Which uses FMC_D0 to FMC_D7 and FMC_A0, same data and 1 address lines as above)

Is it possible to have the LTDC continuously refreshing the display from the SDRAM, and then temporarily "pause" the SDRAM access to use the FMC bus to perform a read from the 8080 interface on a different bank?

My understanding is that the FMC should handle this by using the different Chip Select lines (SDNE0 and NE1). However, I'm concerned about the practical implications:

1. What is the correct software procedure to switch the FMC's context from SDRAM to the 8080 interface and back again without corrupting the SDRAM or causing a system crash? as both of this shall happen cyclically
2. Will this on-the-fly reconfiguration cause the LTDC to lose synchronization, resulting in flicker or tearing on the display?
3. How can I ensure that the SDRAM data is preserved during the time the FMC is busy with the 8080 read?

[mƎALLEm · Accepted solution]

Hello,

The switching between chip selects are handled automatically by hardware (CPU/AHB/FMC) according to the address from which you are reading/writing from/to. It's transparent to the user. Example if you access to 0xCxxxxxxx, the FMC will enable the SDRAM chip select while PSRAM NE1 is disabled (High level). Same case, if you access 0x6xxxxxxx, NE1 will be activated (low level), SDRAM chip select will be disabled.

I'm not expert of LTDC interface but I think it depends on the system performance and the refresh of the LCD and the display size. Better to do the tests.