Problems Writing to SDRAM When Sharing FMC Data Lines with 8080 Interface

[joezzaghari]

Hello,
We are working with an STM32F429ZIT6TR to design an 800x480 LCD Display Controller Board,
I configured the FMC with the 8080 interface to receive data from Main Board (another provider), and also enabled SDRAM through the FMC. The LTDC is used to drive the LCD.

The plan is to transfer data to our Display Controller board via the 8080 interface and then use the LTDC for display refresh. The data lines are shared between the 8080 interface and the SDRAM, but they have different chip select signals.

we built a first prototype, but when we tried to write data into the SDRAM, we observed sporadic/incorrect values.

My questions are:

1. Could sharing the data lines between the 8080 interface and SDRAM cause signal integrity or bus contention issues, even though the chip selects are different?
2. Do you have any recommendations for PCB layout in this case?

[mƎALLEm]

Hello,

As you said it's managed by different chip select signals. The chips select is enabled by device at a time. 

Did you monitor the chip selects using an oscilloscope or a logic analyzer?