Artifacts on Newhaven ASXP Migration - Is it SW, Custom PCB, or a Panel Defect?

[Trampler]

Hello everyone,

I am currently migrating a project from a Newhaven ATXL series display to their newer ASXP series (both 4.3", 480x272 RGB interface) on a custom board based on the STM32F767.

I am trying to isolate the root cause of severe color artifacts I'm seeing, specifically whether this is a Software configuration issue, a signal integrity issue on my Custom PCB, or a potential hardware defect in the display panels I received.

The Situation: I have configured the LTDC timings strictly according to the new ASXP datasheet. However, the image is unstable and has artifacts.

The "Hot-Swap" Verification: To troubleshoot, I performed a live test to rule out my PCB connections:

1. I initialized the STM32F767 with the new ASXP LTDC settings.

2. Connected the new ASXP screen -> Result: Artifacts/Noise.

3. While powered on, I swapped it with the old ATXL screen.

4. Result: The old ATXL screen works perfectly even when driven with the new ASXP timings.

Video of the test:

My Question: Since the old screen works fine with the new settings on the same PCB, I am confused about the source of the failure with the new screen.

• Software: Is the ASXP series significantly more sensitive to DCLK Polarity or Drive Strength than the ATXL?

• Hardware (PCB): Could my custom PCB design be marginal for the newer ASXP controller?

• Defect: Given that the settings work on the old screen but fail on the new one, is it possible that these specific ASXP units are defective?

Has anyone experienced a case where a newer panel is this much more sensitive to signal quality, or should I suspect a bad batch of displays?

Any advice to help me pinpoint the culprit would be appreciated.

Thanks.

[ahsrabrifat]

Your test strongly suggests panel-specific sensitivity. The ASXP series often needs stricter timing and polarity. It also reacts more to signal integrity issues than the older ATXL panel. You can review related STM32 design notes here:

https://www.pcbway.com/blog/PCB_Design_Tutorial/Tutorial__How_to_Design_Your_Own_Custom_STM32_Microcontroller_Board.html

Try flipping DCLK polarity first. Also try enabling DE mode. These changes often fix sampling errors. Small porch changes can also help. Reduce drive strength if edges look harsh. Add tiny series resistors if ringing appears.

If none of that helps, suspect the panel batch. Your hot-swap test supports this idea. The ATXL works under the same setup. A second ASXP unit can confirm this.

[Trampler]

Thanks for the suggestions. Regarding the hardware, I strictly followed ST's design guidelines and datasheets during the PCB design, so I believe the layout is within spec. I have also already tried changing DCLK polarity and drive strengths with no luck.

My main question is about enabling the "DE Mode" you mentioned. As the datasheet indicates, HSYNC and VSYNC need to be grounded for this mode. Since the STM32 LTDC generates these signals by default, how is this typically handled on the MCU side? Should I just configure the HSYNC and VSYNC pins as GPIO Output Low (GND) instead of their LTDC Alternate Function while keeping the LTDC enabled for data and DE? I wasn't sure if there's a specific register setting or if forcing the pins Low via GPIO configuration is the standard way to achieve this.