SPC560D40x - Interrupt Duration

[Binbin Zhang]

Posted on May 03, 2017 at 05:45

Hi ST expert,

I am trying to use SPC5 as a multi-channel PWM controller. Normally for this kind of application, the duty cycle calculation will be done in an interrupt. For 100kHz PWM, the allowed interrupt duration is <10uS, for example 8uS max. The rest of time (10uS-8uS=2uS) should be reserved for other processes, such as communication etc.

As there is a lot calculation for multi-channel PWM, it is necessary to maximize the usage of the interrupt duration. However, I found it will take >1.2uS to enter an interrupt and take another 1uS to go back to the main routine for 48MHz clock. That means >40% of the interrupt duration will be wasted. Attached is my program used to test the interrupt duration and the captured waveform - PIT Channel 1 as the trigger source; PC9 is the output.

My question here is why SPC5 needs so many clocks to enter and left the interrupt and is there any way to reduce such unnecessary timing?

Thank you!

#intc

[Erwan YVIN]

Posted on May 04, 2017 at 09:43

Hello BinBin ,

I am checking with Application team.

did you use RLA / HAL / your own interruption handler?

    Best regards

                    Erwan

[Binbin Zhang]

Posted on May 04, 2017 at 10:22

Hello Erwan,

Thank you for your help.

I tried both RLA and HAL interruption handler and the result is the same. I found this problem when I worked on a program at eMIOs OPWMB mode. Later I verified it with PIT interruption. Attached herewith is my simple program and its result for your reference.

Thank you again and look forward to your reply.

Best Regards,

ZHANG Binbin(张斌斌)

Goldpower Tech Pte Ltd

Tel: +65-6294 7577

Fax: +65-6294 7477

________________ Attachments : PIT1_ISR.txt.zip : https://st--c.eu10.content.force.com/sfc/dist/version/download/?oid=00Db0000000YtG6&ids=0680X000006Hygg&d=%2Fa%2F0X0000000bAv%2Fe74NsdKPS1UJz4_mwIr595q8TKA.C2BATlNhpnXWlBI&asPdf=falseISR_Timing.pdf : https://st--c.eu10.content.force.com/sfc/dist/version/download/?oid=00Db0000000YtG6&ids=0680X000006Hygb&d=%2Fa%2F0X0000000bAw%2F0h09Rp47XH5fYdbdkMiLiiXZJV0Y2n6DSazqvtGmdRU&asPdf=false

[Binbin Zhang]

Posted on May 29, 2017 at 02:26

Please follow-up this subject. 

Thanks!

[Tesla DeLorean]

Posted on May 29, 2017 at 02:59

You might want to review the assembler code emitted by the compiler, and architectural details of the micro-controller.

[Binbin Zhang]

Posted on May 29, 2017 at 10:40

I tried to use UDE STK 4.8 to view the code. It showed that every interruption end with the following code:

IRQ_EPILOGUE();

} 0x000029B4: C5 01 SE_LWZ R0,0x14(R1) 0x000029B6: 00 90 SE_MTLR R0 0x000029B8: C3 F1 SE_LWZ R31,0xC(R1) 0x000029BA: 20 F1 SE_ADDI R1,0x10 0x000029BC: 00 04 SE_BLR

Then jump to 0X0000011A:

0x0000011A: 7C 00 06 AC MBAR 0x0

0x0000011E: 70 7F E7 F4 E_LIS R3,0xFFF40x00000122: 70 70 C0 18 E_OR2I R3,0x80180x00000126: D0 33 SE_STW R3,0x0(R3)_ivor_exit:0x00000128: 18 01 10 20 E_LMWVGPRW 0x20(R1)0x0000012C: 18 21 10 10 E_LMVSPRW 0x10(R1)0x00000130: 18 81 10 08 E_LMVSRRW 0x8(R1)0x00000134: 18 21 80 50 E_ADDI R1,R1,0x500x00000138: 00 08 SE_RFI

Is there any way to view the code before entering the interruption?  Is there any way to shorten the entering and ending duration (> 2uS) for all the interruption?

[Erwan YVIN]

Posted on June 14, 2017 at 10:31

Hello Binbin ,

The Interrupt handler is managed in ivor.s

(Cf Code below)

_IVOR4:
 SAVE_CONTEXT
 /* Software vector address from the INTC register.*/
 e_lis %r3, HI(INTC_IACKR_BASE) /*IACKR register address. */
 e_or2i %r3, LO(INTC_IACKR_BASE)
 se_lwz %r3, 0(%r3) /* IACKR register value. */
 se_lwz %r3, 0(%r3)
 se_mtCTR %r3 /* Software handler address. */
 /* Restoring pre-IRQ MSR register value.*/
 mfSRR1 %r0
 /* No preemption, keeping EE disabled.*/
 se_bclri %r0, 16 /* EE = bit  */
 mtMSR %r0
#if (OSAL_ENABLE_IRQ_PREEMPTION == TRUE)
 /* Allows preemption while executing the software handler.*/
 wrteei 1
#endif /* OSAL_ENABLE_IRQ_PREEMPTION */
 /* Executes the software handler.*/
 se_bctrl
#if (OSAL_ENABLE_IRQ_PREEMPTION == TRUE)
 /* Prevents preemption again.*/
 wrteei 0
#endif /* OSAL_ENABLE_IRQ_PREEMPTION */
 /* Informs the INTC that the interrupt has been served.*/
 mbar 0
 e_lis %r3, HI(INTC_EOIR_BASE)
 e_or2i %r3, LO(INTC_EOIR_BASE)
 se_stw %r3, 0(%r3) /* Writing any value should do. */
 RESTORE_CONTEXT
 se_rfi�?�?�?�?�?�?�?�?�?�?�?�?�?�?�?�?�?�?�?�?�?�?�?�?�?�?�?�?�?�?�?�?�?�?�?�?�?

Could you increase PWM Interrupt priority and enable OSAL_ENABLE_IRQ_PREEMPTION (cf OSAL Component)?

Best regards

Erwan

[raghu tumati]

Posted on September 20, 2017 at 19:05

Hi Binbin

I think I am having a similar problem using the PIT. I am trying to generate a timer interrupt every 1.7uS to toggle a GPIO and it does not seem to be working. In fact any timer setting <4us is quite unstable and I cannot get the timer to interrupt < 2.5uS. The lowest setting for a stable timer I can get is ~5us. 

I believe it is because of the number of cycles its taking to get to the ISR and back. 

Were you able to solve the problem by giving it a higher interrupt priority or any other way?

Thanks