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I2C bus lockup (SDA held low) involving ISM330 and IIS2MDC

L-li
Associate II

Problem description:

We are seeing a hard I2C bus lockup involving an ISM330 IMU and an IIS2MDC magnetometer on the same bus.

 

The failure mode is that SDA is driven low permanently, and the bus cannot be recovered by standard I2C recovery procedures (9–20 SCL pulses with SDA released).

 

This occurs both immediately after MCU firmware is flashed and during nominal runtime, seemingly at random.

 

Once the condition occurs, a full MCU reset does not recover the bus. On a bench setup we confirmed by probing that SDA is physically held low.

 

Hardware configuration:

MCU: STM32 acting as I2C master

Devices on bus:

  • ISM330 (IMU)
  • IIS2MDC (magnetometer)

These are the only slaves on the bus.

Standard I2C pull-ups are used, with no level shifting.

 

I've done additional testing to try to find the problematic device by removing devices and reconfiguring connections (auxiliary I2C), see results below.

 

Observed behavior by configuration:

  • ISM330 only on I2C: no issues
  • ISM330 and IIS2MDC directly on MCU I2C: SDA eventually stuck low and not recoverable
  • IIS2MDC only on I2C: no issues
  • ISM330 and IIS2MDC via auxiliary I2C (SDx and SCx): same failure occurs, but sometimes recoverable by clocking

During failure, probing shows both main SDA and SDx (when using auxiliary I2C) are held low

 

In the direct-connection case, forced SCL clocking (9–20 pulses) does not release SDA.

In the auxiliary I2C case, forced clocking sometimes recovers the bus, but the fault still occurs.

 

Key observation:

  • Based on the testing, having the combination of both devices directly on the I2C bus causes lock up.
  • Neither of the devices alone ever locks up the bus.
  • When both devices are present, the bus can be locked up until devices are power cycles.

 

Questions for ST engineering:

  1. Is IIS2MDC known to hold SDA low under any fault condition such as mid-transaction reset, brownout, internal state machine stall, or clock stretching related issues?
  2. What exactly does the ISM330 sensor hub do on SDx when a downstream slave is stuck? Does it actively generate clocks, reset the I2C state machine, or tri-state the SDx line?
  3. Is auxiliary I2C expected to be more tolerant of a misbehaving slave than direct I2C connection?
  4. Is there a documented or recommended recovery sequence, such as register writes, reset commands, or power cycling order, to force IIS2MDC to release SDA once it is stuck?
6 REPLIES 6
TDK
Super User

Look at the SDA/SCL on a logic analyzer and see what happens when SDA gets stuck low.

CS lines are driven high?

SCL line remains free when SDA is stuck low?

 

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L-li
Associate II

CS lines are driven high?


CS lines are pulled high in the circuit.


SCL line remains free when SDA is stuck low?


SCL line is free when SDA is stuck low. As mentioned in the post, I've also tried clock it out in the direct I2C configuration with no luck but with the aux I2C configuration it was able to recover.

Anything I should try and test?

I think you need a logic analyzer to see what's going on. Slaves are not allowed to hold 0 on SDA indefinitely. What is the bus master?

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L-li
Associate II

I have hooked up a logic analyzer and that's how I found SDA was held low. I've attached a screen clipping of the SDA being held low and the activity on the SCL line is an attempt to clock out the line.

The bus master is a STM32. Additionally when I power down the STM32, the SDA remains low so I don't think the STM32 is holding it low.

TDK
Super User

Maybe I could have been more clear. I meant looking at the bus at the time SDA becomes stuck. The hope is that you can identify an event or transaction or some other bus error that causes the issue. And see if that is repeatable. Even if the master is not holding SDA low, it may be doing something it shouldn't to cause the slave to misbehave.

> The bus master is a STM32

It would be helpful to be more specific. There are many different families with a handful of different I2C implementations among them. Some of these families have I2C related errata.

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L-li
Associate II

OK thanks for clarifying that, I'll work on recreating the issue and getting a scope trace.


It would be helpful to be more specific. There are many different families with a handful of different I2C implementations among them. Some of these families have I2C related errata.


The STM32H723ZG, lmk if you need more detail.