Hi all, (STM32U575..) we have the SRAM2 ECC active on reset by the according configuration of the flash option byte. For testing purpose I switch off the ECC by using the HAL_RAMCFG_StopECC(&hramcfg_SRAM2), manipulate one cell for a one bit error and...
hiI am currently working on a project that utilizes the STM32H753 to acquire images through an image sensor called AR1034.However, the size of the image I am acquiring is 1280*960. Due to the large size, it is not possible to store it inside the MCU,...
uC: STM32H725AEIToolchain / IDE: STM32CubeIDECubeMX version: 6.8.0I'm using CubeMX for code generation with HAL drivers.I'm currenty receiving a JPEG from a camera via DCMI with 640x480.I'd like to step up the game to 1280x960, but the picture would ...
Hi @all,we have an application, where we use the LSE. In due to weaknesses of the part we use, the LSE can fail sometimes.If I then use the __HAL_RCC_BACKUPRESET_FORCE() and __HAL_RCC_BACKUPRESET_RELEASE() to reset the LSE and LSI system, also the SR...
Hello,for determining the Stack-Utilization I fill it with 0xDADBEEF. If you have recommendations and other ideas, I’d like to know and looking forward to learn from others, how they approach the issues “Stacksize” and “Stackutilization”.Code for the...
Reference documents: STM32H755 reference manual - RM0399, ECC implementation guide for STM devices - AN5342I have been implementing a handler for errors triggered by RAMECC on an STM32H755 Nucleo dev board. Testing of the handler has been conducted b...
For a specific task at my workstation, I need to cache a variable before the watchdog reset and query it again after the reset. For this I have implemented a timer that writes the variable to RAM just before the watchdog. For this I defined according...
Hello,I am using the STM32F756ZGT6 for an upcoming project. I am using a 480x272 resolution display (RGB565) with a single layer. I also have additional features that will be on this board that use more RAM (2 tasks, multiple variables, etc.) that a...
I'm essentially trying to swap the RAM modules between the two cores on the STM32H755 so that all data in RAM used by the M7 is in SRAM1-3 and for the M4 is in AIXISRAM, but I'm observing some issues in startup behavior on the M4.From my understandin...
STM32F407VG has 4kB of backup SRAM that's preserved when VDD is removed if VBAT is present. A few other MCUs in the STM32F40x line have that feature too.Do any MCUs outside of the STM32F40x line have SRAM that's preserved with VBAT? Is there a way ...