As per errors in AN2606 and this thread https://community.st.com/t5/stm32-mcus-products/stm32h5-bootloader-uses-usart-pins-that-do-not-match-roles-in/m-p/594610#M224078 I need the correct pins that STM32H563/STM32H573 use for USART1/2/3 and FD-CAN bo...
STM32H5763IIK, Bootloader v14I'm planning on using USART1 and USART3 in my application. I'd like to be able to access the bootloader from both. The bootloader documents say that USART2 and USART3 at very least use pins that are not attached to their ...
Controller is STM32G4CETx , Flash is configured to use dual bank mode.I have checked the errate sheet issue 2.2.2 about problems with the data cache in this situation, but it is still not clear to me, why stepping over the __ISB instruction causes a ...
In the installed STM32Cube Repository there are hundreds of application notes and data sheets, does anybody know where there is a list of contents? It would take a long time to open them all to check or get the right grep phrase to search.
I'm trying to configure the Bootloader for a STM32G4A1KE processor, but in the AN2606 I cannot find any information regarding this processor (family STM32G41). Although it is listed in the introduction section of AN2606, no further information is gi...
Hi, I'm using a STM32G07x1 that will need to receive firmware updates from an embedded Linux CPU. The only connection between these devices is an I2C bus so I plan to use the ROM I2C bootloader to handle updates.I am aware of AN4221 that describes ho...
Hi, I was reading the document "DS13867 Rev 3" (datasheet for STM32C031x4/x6) (https://www.st.com/resource/en/datasheet/stm32c031c6.pdf), and while searching about pin PF3, I found this strange information saying that it is a "Supply" pin type. I've ...
Hi! Noticed a typo in the system configuration controller (SYSCFG) register map in both reference manuals RM0399 (Rev 4) and RM0433 (Rev 8). The SYSCFG_CCCR register is at two different offsets (0x28 and 0x2C) and SYSCFG_PWRCR is missing. I think, S...
Hi i have a generic doubt about falsh wait states:Say we configured the PLL to run system core clock at 160 M Hz, with flash wait states as 5.Then is cpu is equvilent to 32 MHZ core performance? (assuming 1 clk/ 1 inst, no ART's)Could some one help m...
