Since in the RM0483 Reference manual SR5E1x 32-bit Arm® Cortex®-M7 architecture microcontroller for electrical vehicle applications, I read the following paragraph:
Platform RAM controller AXI (PRAMC_AXI)
"15.7 Exclusive monitor
The local monitor enables the RAMs to be used for semaphores between processes
running on different masters. The local monitor exclusive granule size is 8 bytes.
A load exclusive transaction on the bus marks a 64-bit memory region as exclusive. A store
exclusive passes the local exclusive monitor check if it accesses the same 64-bit memory
region and returns the exclusive monitor to open access state. If a store exclusive accesses
an address outside the marked 64-bit region, then the store exclusive instruction fails the
exclusive monitor check and the monitor is returned to open access state.
There are multiple exclusive monitors to enable it for multiple masters. The number of
exclusive monitors is controlled by NUM_PROCESSORS.
15.7.1 Support for Exclusive monitor behavior
15.7.1.1 Features
• Support exclusive requests aligned to local monitor concept as specified in Arm Core
• Exclusive reservation granularity would be 64 bytes
• Support one exclusive monitor per processing element
• Aligned with the implementation as defined in Arm architecture reference manual ARMv8_A for Exclusive monitor"
I supposed that the implementation of SRAM spinlocks was possible for SR5E1x MCUs, but when I try to start an "exclusive transaction" with
ldrex %0, [%1]
...
: "=&r"(tmp) : "r"(p_lock) : "memory", "cc"
I get a BusFault
The p_lock=0x240034A8 and the MPU is enabled with region 5 è configured in the following way: rbar5 0x24003405 e rasr5 0x130C0011. That should mean: region covering 512 bytes from 0x24003400, with attributes SHAREABLE, NOT CACHEABLE, BUFFERABLE, NOT EXECUTABLE
I start to fear that the memory transition to start the exclusive transaction should have been done at 64 bytes, but this is not possible in Cortex-M AFAIK since it would require ldrexd instruction that is not available.
Obviously the code seems to work if MPU is turned-off, since the monitor do not start the transaction and indeed, the tests that I have for spinlocks shows that mutual exclusion between cores is not achieved in that case.
Could you please provide some insight about this behavior?
