I'm working on porting FreeRTOS to the SPC58EC80C3 microcontroller (SPC58EC-DISP discovery board) and would appreciate any guidance on how to manually add a port for this device to the latest FreeRTOS release.
Specifically, I'm looking for any existing steps or best practices to configure FreeRTOS for this architecture, given its e200z4 core and e200z0 core.
Additionally, I'm trying to understand if it’s possible to configure FreeRTOS to run on core 0, or if we are limited to using core 2 for real-time tasks and FreeRTOS functionalities. Any input on setting up the context-switching mechanisms, configuring tick interrupts, or handling inter-core communication in FreeRTOS would be highly appreciated.
I came across a section of code in `portasm.s` related to core definitions on single-core devices:
/* * This is a temporary workaround to fix core definition on single-core devices. * On single-core devices, the boot core is CORE_0, but in boot.s, the IVOR * definitions used lack the "C0_" prefix, causing an issue. * To avoid modifying boot.c, a simple workaround is applied here to redefine * the configUSE_CORE_x definitions for this file. * * TODO: Resolve this by appropriately redefining CORE IVORs definitions. */
From this, it appears that core 2 is currently set as the default for running FreeRTOS, even on single-core setups. Does this mean we are effectively limited to using core 2 for FreeRTOS on SPC58EC80C3, or is there a planned update that would allow for running FreeRTOS on core 0? Clarification on whether core 0 can be configured for FreeRTOS would be greatly appreciated, as well as any recommendations for managing core-specific tasks, context-switching, and tick interrupts.
Thank you for any insights or upcoming updates on this issue!
Yes, theoretically you can run both core with FreeRTOS.
You need to generate 2 different AutoDevKit Studio projects completely separated one from the other, and core 2 that starts first should activate core 0 (unless you also want to change the boot-up sequence and let both cores start together).
Once you generate the .elf file for the core 0, you should manually load it in an appropriate FLASH partition that has to be unique for each core.
If you need the two cores to synchronize, then you should create semaphores on shared memory areas.
It is possible but it requires a lot of manual activities...
