Why are some I/O pins on stm32f303 permanently pull-up under reset?

[sadeghzadeh78]

Due to stm32f303rct6 refrence manual (RM0316) p. 243, the reset value of GPIOA_PUPDR register for PA8 and PA11 are equal to 00. This means that the output of them are not pull-up or pull-down under reset state,

but

In my practical test, PA8 and PA11 are permenetly pull-up.

How to justify that? or

What is the problem with my test?

[TDK]

> In my practical test, PA8 and PA11 are permenetly pull-up.

Maybe describe your hardware and test and explain why you think they're pulled up.

[sadeghzadeh78]

Thanks for attention!

I disconnected uC pin routes to my hardware and then put the oscilloscope probe on these pins under reset state. Then they remain HIGH.

If I connect uC pin to the 10 KOhm pull down resistor, its voltage reaches about 0.6 Volts and similarly for 4.7 KOhm is 0.36 Volts.

The above test aproves that 3.3 V (VCC voltage) are divided by a resistor divider with the internal pull-up resistor equal to 40 KOhm ( also this value mentioned by stm32f303rct6 datasheet ).

[TDK]

Well that’s a good test. I can’t see why it’d be doing this, barring a hardware issue or a documentation error. Maybe initialize them as input with pull down to verify they go all the way to 0V without issue.