What is the reason for have two SRAM in the STM32L476 microcontroller?

[arnold_w]

I'm learning about the STM32L476 microcontroller and saw that it has two SRAM memories. What is the reason for that? I also see that it's possible to enable parity check on SRAM2. How come, is SRAM2 unreliable?

[TDK]

No memory is 100% reliable. Having a parity bit allows for the detection of errors if only a single bit is flipped. Some applications have requirements for redundancy or error checking due to safety and the addition of a parity bit can satisfy those requirements.

https://en.wikipedia.org/wiki/Single-event_upset

[KBuch]

The datasheet is your friend.

SRAM2 is a 32kByte memory area which can retain its content even if you send the processor into standby mode (with extremly low power consumption).

When powering up you want to make sure that the memory has not changed to to unforseen external reasons.

[KnarfB]

Just another aspect: You may put some code to SRAM2 and execute it with "with maximum performance ... thanks to access through ICode bus." (Ref.Manual) Looking at the bus matrix and memory mapping you will see data in SRAM1 is accessed via SBus and both can be done in parallel.

hth

KnarfB

[Uwe Bonnes]

Seperate RAM regions allow concurrent RAM access, e.g. by DMA and the CPU