Timing information for OCTOSPI interface with free running clock

[RIvo.1]

Hi,  

Where can find timing information for the octospi (8-bit SDR) interface with free running clock enabled ?

Couldn't find it on the device datasheet (STM32H730VB). I'm especially in need of the timing between SCK e nCS when free running clock is enabled.

[Amel NASRI]

Hi @RIvo.1​ ,

May you provide more details about your use-case with the free running clock?

I ask this because it is expected to enable free running clock with the Delay Block in order to calibrate the OCTOSPI clock.

Once the calibration is done, the generated clock by the Delay Block is used and the free running clock should be disabled.

-Amel

[RIvo.1]

Hello Amel,

I need to update a design that uses a [FPGA + FSMC@F405] to [FPGA + OctoSPI@H730].

The current changes we made in our product would need more IO pins from the fpga but can't change the packages from QFP (assembly cost restrictions).

In my application I have to transfer about 3Kbytes (6 blocks of 512 bytes) in 100us every 1ms ( about 30MB/s ) so speed is not THAT much a concern when moving to OctoSPI. To keep the board design simply as possible, i intend to use a 40MHz clock.

If possible, using the free running clock would allow me use a fully synchro design and remove almost all CDC logic from the fpga design minimizing the transactions overhead. I'm still (manually) assembling the prototype board for the new design so i couldn't probe the signals yet. That's why i asked about the documentation.

By the way, i do have a reference clock from PLL2 of H730 via MCO2 to the fpga... Maybe i could be be able to synchronize the fpga pll clock to the OctoSPI root clock and use DQS + Delay Block to compensate the jitter.

Best regards,

Rodrigo.