Timer Interrupt for 1ms

[er_it]

Posted on March 30, 2015 at 14:16

I am using STM32F207 VG controller for my learning.I have few following doubts.

I want to use timer for up counting.Timer clock is set to 36 MHz.I want to generate timer interrupt for every 1 ms.

With what values i need to set up ''TIM_TimeBaseInit'' funstions.I mean to ask what should be the value of following parameters.

uint16_t TIM_Prescaler;        

  uint32_t TIM_Period;      

  uint16_t TIM_ClockDivision;    

  uint8_t TIM_RepetitionCounter;

Thanks in advance :) !!!

[Tesla DeLorean]

Posted on March 30, 2015 at 14:28

ClockDivision and RepetitionCounter should be set as defaults.

Period and Prescaler are factors, divided against the source clock, and written in N-1 form.

1ms = 1KHz

36000000 / 1000 = 36000

1 x 36000 = 36000

Prescaler = 1 - 1; // DIV1 (smaller)

Period = 36000 - 1; //DIV36000

[er_it]

Posted on March 30, 2015 at 14:38

hi,

Thanks for the quick response.I have got the point how u have calculated Period(Timer clock source frequency divided by 1ms).But How prescaler value comes out to be 1?

what is the mathematical relation between Prescaler,Period and timer clock source?

Thanks

[Tesla DeLorean]

Posted on March 30, 2015 at 15:01

Freq = TIMCLK / ((Prescaler + 1) * (Period + 1))

The FACTORS could be 36 x 1000, 360 x 100, etc. The limit for Precalers is always 16-bit, the Period can be 16-bit or 32-bit depending on the STM32 and TIMx. Generally you want the Period to be the larger of the two.

Freq = 36000000 / (1 * 36000)

Freq = 1000 (HZ)

PeriodInSeconds = 1 / 1000

PeriodInSeconds = 0.001 (SECONDS)

[er_it]

Posted on March 31, 2015 at 15:07

Hi,

Thanks For the response :) !

I need some more help.I am looking into a code.Kindly see below the code snippet.

int main(void)

{

 WatchDog_clear();

  Watchdog_Init();

  Clock_config();

  Timer2_init(); 

    ....

    ....

}

where    ''Clock_config() '' is :

bool Clock_config(void)

{

    bool retVal = false;

    

    //define all system clocks

    ErrorStatus HSEStartUpStatus;

    

    /* RCC system reset(for debug purpose) */

    RCC_DeInit();

    

    /* Enable HSE */

    RCC_HSEConfig(RCC_HSE_ON);

    

    /* Wait till HSE is ready */

    HSEStartUpStatus = RCC_WaitForHSEStartUp();

    if(HSEStartUpStatus == SUCCESS)

    {

        /* HCLK = SYSCLK */

        RCC_HCLKConfig(RCC_SYSCLK_Div1); 

        

        /* PCLK2 = HCLK */

        RCC_PCLK2Config(RCC_HCLK_Div1); 

        

        /* PCLK1 = HCLK/2 */

        RCC_PCLK1Config(RCC_HCLK_Div2);

 

 /* Enable Prefetch Buffer */

//  FLASH->ACR |= FLASH_ACR_PRFTBE;

     

        FLASH->ACR = FLASH_ACR_PRFTEN | FLASH_ACR_ICEN | FLASH_ACR_DCEN | FLASH_ACR_LATENCY_3WS;

     /* Flash 2 wait state */

    //  FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);

    //  FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_2;

      

        

        /* Configure PLLs */

    //    RCC_PLLConfig(RCC_PLLSource_HSE_Div2, RCC_PLLMul_9);

        RCC->PLLCFGR = PLL_M | (PLL_N << 6) | (((PLL_P >> 1) -1) << 16) |

                   (RCC_PLLCFGR_PLLSRC_HSE) | (PLL_Q << 24);

        

        /* Enable PLL */ 

        RCC_PLLCmd(ENABLE);

    

        /* Wait till PLL is ready */

        while(RCC_GetFlagStatus(RCC_FLAG_PLLRDY) == RESET)

        {

        }

        /* Select PLL as system clock source */

        RCC_SYSCLKConfig(RCC_SYSCLKSource_PLLCLK);

        

        /* Wait till PLL is used as system clock source */

        while(RCC_GetSYSCLKSource() != 0x08)

        {

        }

        retVal = true;

    }

    else

    {

        /* If none of the define above is enabled, the HSI is used as System clock

        source (default after reset) */ 

        /* Disable HSE */

        RCC_HSEConfig(RCC_HSE_OFF);

 

 /* Enable Prefetch Buffer */

//  FLASH->ACR |= FLASH_ACR_PRFTBE;

     /* Flash 2 wait state */

    //  FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);

    //  FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_2;

/* Configure Flash prefetch, Instruction cache, Data cache and wait state */

    FLASH->ACR = FLASH_ACR_PRFTEN | FLASH_ACR_ICEN | FLASH_ACR_DCEN | FLASH_ACR_LATENCY_3WS;

      //  RCC_PLLConfig(RCC_PLLSource_HSI_Div2, RCC_PLLMul_9);

           /* Configure the main PLL */

    RCC->PLLCFGR = PLL_M | (PLL_N << 6) | (((PLL_P >> 1) -1) << 16) |

                   (RCC_PLLCFGR_PLLSRC_HSE) | (PLL_Q << 24);

        RCC_PLLCmd(ENABLE);

        /* Wait till PLL is ready */

        while (RCC_GetFlagStatus(RCC_FLAG_PLLRDY) == RESET)

        {

        }

        /* Select PLL as system clock source */

        RCC_SYSCLKConfig(RCC_SYSCLKSource_PLLCLK);

        /* Wait till PLL is used as system clock source */

        while (RCC_GetSYSCLKSource() != 0x08)

        {

        }

    }

    RCC_APB1PeriphClockCmd(

          RCC_APB1Periph_I2C1

          | RCC_APB1Periph_I2C2

          | RCC_APB1Periph_USART2

          | RCC_APB1Periph_UART5

          | RCC_APB1Periph_UART4

         // | RCC_APB1Periph_SPI3

           

          | RCC_APB1Periph_TIM2

          | RCC_APB1Periph_TIM3

          | RCC_APB1Periph_TIM4,

        ENABLE

        );

    

    RCC_AHB1PeriphClockCmd(

          

           RCC_AHB1Periph_GPIOA

          | RCC_AHB1Periph_GPIOB

          | RCC_AHB1Periph_GPIOC

          | RCC_AHB1Periph_GPIOD

          | RCC_AHB1Periph_GPIOE,          

        ENABLE

        ); 

    return retVal;

}

and Timer2_init() is :

void Timer2_init(void)

{

  TIM_DeInit(TIM2);

  /* Time base configuration TIMER2*/

  //TimerClock=36Mhz; 1/36e6 = 2.77e-8 ; it takes 0x8CA0 ticks to reach 1ms; prescaler N=1, CLK/(N+1)

  TIM_TimeBaseStructure.TIM_Period = TIMER_MAIN_1MS_VAL; 

  TIM_TimeBaseStructure.TIM_Prescaler = 2;

  TIM_TimeBaseStructure.TIM_ClockDivision = 0;

  TIM_TimeBaseStructure.TIM_CounterMode = TIM_CounterMode_Up;

  

  TIM_TimeBaseInit(TIM2, &TIM_TimeBaseStructure);

  TIM_SelectMasterSlaveMode(TIM2, TIM_MasterSlaveMode_Enable);

  TIM_SelectOutputTrigger(TIM2, TIM_TRGOSource_Update);

  .

 .

 .

}

Person who has written the code put in comments(Highlighted part in red) that timer clock is 36MHz. Now my question is i don't understand how Timer Clock (commented Part Highlighted in red) comes out to be 36 MHz?

[Tesla DeLorean]

Posted on March 31, 2015 at 16:37

I need some more help.I am looking into a code. Kindly see below the code snippet.

Well that's going to depend a lot of all the defines you haven't supplied, and the external clock source frequency, right?

If we assume you have an STM32F10x device, clocking at 72 MHz, the APB2 runs at 72 MHz (DIV1), and the APB1 runs at 36 MHz (DIV2), while TIM's on APB1 will run at 2X that, so 72 MHz, per the Clock Tree diagram in the Reference Manual.

I can't get in the head of the person who wrote the comment/code. Does the code in fact generate a 1 KHz (1ms) clock, or not? Check on scope, or other measurement of the time base.

If we assume the TIM clock here is 72 MHz, the prescaler needs to be 2-1, and the period 36000-1, or some other combination of factors to generate a 1 KHz clock.