stm32R7VI widebus

[semler]

Posted on March 24, 2018 at 10:29

I met an interesting problem. When I tried to configure this IO with SD widebus config (4bit) with hal libraries I always failed with initialization because pin 1 of SD card is on logic 0.

The solution was firstly let it initialize with pin 1 of SD card as GPIO with logic high as sdmmc core has logic 0 on this pin if it is configured as alternate function and before widebus initialization switch to alternate function.

So it is bug or feature of 4bit mode?

[Tesla DeLorean]

Posted on March 24, 2018 at 15:09

STM32R7VI ??

The code examples for the L4+ parts supporting SDMMC at 4-bit should be viable if correctly wired and no other board level pin conflicts. Code definitely workable on NUCLEO-64 and NUCLEO-144 boards, so look for bugs in your own design/implementation.

The STM32L4R9I-DISCO should work out of the box with provided examples.

http://www.st.com/en/evaluation-tools/32l4r9idiscovery.html

 

[semler]

Posted on March 28, 2018 at 20:23

I quite studied manual for  MCU and specification of SD cards. In sd specification and they recommend pull-ups for pins D0-D3 and CMD pin. However when I look on power-up sequence (page 1670 of reference manual) of SDMMC peripheral, there is something strange I think. Why sets the peripheral all these pins to logic '0' instead of let them hi-z until power stable (and let the pullups do the work) ?

Does the SDMMC peripheal expect that SD card ignores data on these pins during first 74 clock cycles?

This maybe work If you really do power sequencing. Question is if it will work if you have already card on power?

[Tesla DeLorean]

Posted on March 28, 2018 at 20:53

>>page 1670 of reference manual

Can we perhaps establish what part number you're working with, or what specific manual you're looking at? Provide a cite to product page or manual.

Clocking without a chip-select is usually part of clocking the device out of an unknown state, there isn't an async-reset pin here.

[semler]

Posted on March 28, 2018 at 21:07

point is that CS pin is asserted low when is logic 0 on D3 so it is active.

http://www.st.com/resource/en/reference_manual/dm00310109.pdf