STM32L496 SPI 16 clock cycles instead of 8

[RoKsPy]

So I have configured the SPI peripheral with a data frame of 8 bits. However, in the scope, there are 16 cycles in total. The first byte is okay, and outputs the loaded byte, however after the first 8 cycles, there are additional 8 cycles. The issue can be that these unwanted 8 cycles provide some additional, unexpected configuration to the slave.

So I think that the issue is that the SPI is disabled only after the next round of cycles have started because I'm waiting for the transmission level (FTLVL) and busy flag (Status Register BIT7) to clear. The reason I'm thinking of this is that, when I remove the waiting step, SPI runs for the 8 cycles as expected, but also becomes unpredictable at times.

Update: So it wants to send 16 bits regardless if I get it to do 8cycles. For example, I load the buffer with a single byte and manage to output the byte within the 8 cycles after which transmission is stopped. However, the next time I want to send something, there are 8 zeros in front of the next byte, so it will send 8 zeros, and only then it will send the the required byte.

I also tried reducing the baud rate, however, that did not help....

Any ideas?

Many thanks in advance.

[Tesla DeLorean]

Do an 8 bit write to the data register ​

[RoKsPy]

I'm already writing it with the uint8_t data type

[TDK]

To write a byte:

*((__IO uint8_t *) SPIx->DR) = value;

https://github.com/STMicroelectronics/STM32CubeL4/blob/5e1553e07706491bd11f4edd304e093b6e4b83a4/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_spi.c#L951

[PMish.1]

This worked for me.

However "&" is missing in this comment. It should be something like (as in the link provided)

*((__IO uint8_t *)&SPIx->DR) = value;

[waclawek.jan]

Write a minimal but complete compilable example exhibiting the problem, and post.

JW