STM32L431 Spurious RESET on recent component batches

[sroll]

Hi,

when i use sleep mode, i have a reset problem on STM32L431CCT6 only on recent batches.

I implemented the workaround described in section 2.2.5 of dm00218224-stm32l431xx-device-errata-stmicroelectronics.pdf but without success.

The problem only affects recent batches (# 948, 950). The previous batches seem ok (n ° 745, 928).

Any ideas?

Regards

[TDK]

Is the reset specifically caused by waking and entering stop mode quickly?

Do the reset bits indicate the cause was a BOR reset or by something else?

[sroll]

the reset is caused by iwatchdog but i don't know why. To have the problem, I must have:

 a stm32 from a recent batch

 SW launched without JTAG

 SLEEP mode activated (every ms in my case).

One difficulty is that when I try to debug and connect JTAG, the problem does not occur.

[Jack Peacock_2]

Check the settings in the option bytes. You may have the flag set to start IWDG immediately after a reset.

Jack Peacock

[waclawek.jan]

> the reset is caused by iwatchdog

IWDG?

How is it set up? How do you refresh it, exactly? How are the clocks managed across the stop mode?

Reduce your code to a minimal complete compilable exhibiting the problem,

JW

[sroll]

Yes IWDG.

The IWDG configuration:

• prescaler:16
• window value:4095
• down-counter reload value 4095

=> reset if no kick since 2s

The IWDG is kicked every second

The SLEEP activation is done with the HAL command: HAL_PWR_EnterSLEEPMode(PWR_LOWPOWERREGULATOR_ON,PWR_SLEEPENTRY_WFI)

The STM32 is configured in external clock mode and the clock is always active

[sroll]

I think the IWDG work well. I removed the IWDG activation from my SW to suppress the reset.

With this code, sometimes the UART stops but the other tasks seem to work well and sometimes all the tasks seem to stop.

I will try to reproduce with a minimal code.

[TDK]

Sounds like IWDG is causing the reset and that it's not spurious.

[waclawek.jan]

> The IWDG is kicked every second

Isn't this the case of unstable LSI, as per ES0318 - Rev 5 2.2.8 Unstable LSI when it clocks RTC or CSS on LSE ?

Can you output LSI somehow, to observe?

JW

[sroll]

I already tried with an IWDG prescalar set to 256 and I still have a reset.

[sroll]

Hi,

I have found the source of my problem. When the STM32 returns from SLEEP (WFI)  mode with mainregulator in lowpower mode the CPU may read an incorrect value from the Flash memory.

The workarround is to call HAL_PWR_EnterSLEEPMode(PWR_MAINREGULATOR_ON,PWR_SLEEPENTRY_WFI) instead HAL_PWR_EnterSLEEPMode(PWR_LOWPOWERREGULATOR_ON,PWR_SLEEPENTRY_WFI) to put the STM32 in sleep mode.

conditions to reproduce the problem

 - STM32L431CCT6 from batch 948 or 950 (batches 745 and 928 are OK. I don't know about the others)

 - the STM32 at 80MHz (10, 20 and 40MHz work well)

 - not launch with JTAG or SWD (I presume JTAG and SWD change the SLEEP mode comportement)

 - call HAL_PWR_EnterSLEEPMode(PWR_LOWPOWERREGULATOR_ON,PWR_SLEEPENTRY_WFI) (every ms in my case)

- generate lots of interrupts (UART trafic at 57600baud in my case)

- wait up to 10mn

I hope it could be useful for someone

[Piranha]

Here is a more useful and simple advice - read the documentation! From RM0394:

Section 5.3.5: The Low-power sleep mode is entered from low-power run mode... When exiting the Low-power sleep mode by issuing an interrupt or an event, the MCU is in Low-power run mode.

Section 5.3.2: To further reduce the consumption when the system is in Run mode, the regulator can be configured in low-power mode. In this mode, the system frequency should not exceed 2 MHz.

And you are complaining that it doesn't run at 80 MHz...