Stm32F7: When is it usefull to enable DCACHE?

[Uwe Bonnes]

Posted on April 12, 2016 at 17:44

In my understanding, DTCM, SRAM1 and SRAM2 all offer single cycle access. This leads my to the conclusion, that enabling DCACHE in a situation where there is no slow external memory does not bring any advantage, but the disadvantage of possible cache incoherencies. Is my understanding right?

Thanks

#cache #performance #stm32f7 #dcache

[Uwe Bonnes]

Posted on April 12, 2016 at 19:41

One reason to enable DCACHE is to cahce access to constant data in flash.  But still please comment on my reasoning about DCACHE for SRMA1/SRAM2 access. DTCM is not cached at all in my understanding.

[Walid FTITI_O]

Posted on April 12, 2016 at 20:01

Hi bonnes.uwe,

DCACHE can be enabled to cache access for all memories related to AXI bus ( not the case for ITCM and DTCM which have 64-bit access). There is no relation between cache enabling and Slow/fast or external/ internal memroies -> Cache always enhance performance in all cases. To prevent incoherence that may happen, you should make write-through operation.

For more details about STM32F7 performance, plesase refere to the application note

http://www.st.com/st-web-ui/static/active/jp/resource/technical/document/application_note/DM00169764.pdf

'' STM32F7 series system architecture and performance'', and you can test the firmware example done with QSPI :

http://www.st.com/web/catalog/tools/FM147/CL1794/SC961/SS1743/LN1920/PF262415

-Hannibal-