STM32F7 - Can not write to FPB registers

[branislav]

Posted on September 25, 2015 at 21:56

Hi All,

During conversion of our debugging code from Cortex-M3/M4 to M7 I run into following problem - it seems that it is not possible to write to any registers in FPB unit, for example FP_CTRL (0xE0002000) or FP_COMP0 (0xE0002008). When attempting to write the value, the register value does not change. Reading from these registers seems to work fine as I see expected value if I use external hardware debugger that sets these registers when breakpoint is set.

I have tried following:

- all this works fine on all STMF3 and STMF4 micros I have worked on

- verified that I'm using word access to these registers by checking generated assembly code

- verified that my code runs in privileged mode by checking value of Control register, I also tried to execute this from interrupt

- verified reading from these addresses if external debugger is setting them. Reading work OK

- tried writing various values, e.g. setting and clearing enable bit in FP_CTRL, verified that I'm writing proper key

- tried writing several FP_COMPx registers

- writing other registers in debugging block works fine, e.g. setting of CoreDebug->DEMCR works OK and I'm able to microstep the code

- checked Cortex-M7 documentation several times, it says that FPB should work the same as on Cortex-M3/M4 (ARMv7-M Architecture Reference Manual)

No matter what I do the value in registers does not change.

If anyone have any suggestions what to try next or what might be the problem I would appreciate it.

Thanks

Branislav

#cortex-m7-stm32-stm32f7-fpb

[Nesrine M_O]

Posted on September 29, 2015 at 14:08

Hi,

The Cortex M3 processor contains a Flash Patch and Breakpoint (FPB) unit that implements hardware breakpoints, and patches code and data from Code space to System space but in the cortex M7, the FPB does not support flash patching. The FP_REMAP register is not implemented and is RAZ/WI.

I'd highly recommend you to take a look to the FPB functional description paragraph in the 

http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.100165_0201_00_en/ric1417175949176.html

 & 

http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.ddi0489b/BABGEDIG.html

-Syrine-

[branislav]

Posted on September 29, 2015 at 18:00

Hi,

Based on my understanding of ARM documents, Flash patching and breakpoints functionality should be independent and I should not need flash patching to use breakpoints. Value in stm32f746 register FP_CTRL on startup is 0x10000080 which indicates that it actually implements 8 breakpoints.

It also seems that SW2STM32 package - eclipse, gdb, openocd and stlink combination is using these registers for breakpoints - I can see expected values written in FP_COMPx registers when I set breakpoints in editor.

if I use external hardware debugger to write to FP_CTRL and FP_COMPx registers I can make the breakpoints trigger too, so it seems that breakpoint functionality actually works. My problem is that I could not make the register values change if I try to set them from application code (as opposed from external hardware debugger).

Branislav

[branislav]

Posted on September 29, 2015 at 18:12

Maybe my problem is related to for some action that needs to happen with these registers I found mentioned in Cortex-M7 spec. But there is not description of them anywhere:

0xE0000FB0

FP_LAR WO - FlashPatch Lock Access Register

0xE0000FB4

FP_LSR RO Unknown FlashPatch Lock Status Register

[branislav]

Posted on September 29, 2015 at 19:34

At the end this has worked for me:

It seems that there is new locking mechanism implemented in Cortex-M7 and each debug block needs to be unlocked first.

For FPB the unlock register FP_LAR is on address 0xe0002fb0 (Cortex-M7 tech ref spec shows incorrect value 0xe0000fb0 and there is no description of register at all).

To unlock FPB on STM32F746 I use this code now:

#define

FP_LAR_UNLOCK_KEY 0xc5acce55

#define

FP_LAR_PTR ((

unsigned

int

*) 0xe0002fb0)

*FP_LAR_PTR = FP_LAR_UNLOCK_KEY;

I found the unlock value in ARM CoreSight Architecture Specification.

All Cortex-M3/M4 that I have worked the unlocking was not required.

Branislav