Skip to main content
jacekborko
Associate II
May 10, 2015
Question

STM32F429 FMC SDRAM DELAY CHANGE

  • May 10, 2015
  • 6 replies
  • 1189 views
Posted on May 10, 2015 at 22:48

The original post was too long to process during our migration. Please click on the attachment to read the original post.
    This topic has been closed for replies.

    6 replies

    stm322399
    Senior
    May 11, 2015
    Posted on May 11, 2015 at 09:48

    Bit changes often appears when refresh is not done frequently enough. Remake the math, or simply test with arbitrary faster value.

    Just make sure that bits other than D13 and D14 are concerned (wait more time), otherwise we cannot exclude a wiring issue.

    jacekborko
    Associate II
    May 11, 2015
    Posted on May 11, 2015 at 20:59

    datasheet says ''Refresh Interval Time  -  max 15.6 '' so :

     //15.6us*84MHz=1311 

    when i use 100

      FMC_Bank5_6->SDRTR=100<<1;

    this didnt gave any result.

    when i put even 

      FMC_Bank5_6->SDRTR=10000<<1;

    thats didnt gave any result.

    ''Just make sure that bits other than D13 and D14 are concerned (wait more time),'' could you explain me this part, and how to check it ?

    Tesla DeLorean
    Guru
    May 11, 2015
    Posted on May 11, 2015 at 21:32

    [DEAD LINK /public/STe2ecommunities/mcu/Lists/cortex_mx_stm32/Flat.aspx?RootFolder=/public/STe2ecommunities/mcu/Lists/cortex_mx_stm32/SDRAM%20STM32F429%20refresh%20problem&FolderCTID=0x01200200770978C69A1141439FE559EB459D7580009C4E14902C3CDE46A77F0FFD06506F5B&TopicsView=https://my.st.com/public/STe2ecommunities/mcu/Lists/cortex_mx_stm32/AllItems.aspx&currentviews=388]See also

    Quantify if, and for how long, the bits hold their correct states? ie measure time to observed failure. If time is zero, consider if it's even wired/soldered correctly.

    Tips, Buy me a coffee, or three.. PayPal VenmoUp vote any posts that you find helpful, it shows what's working..
    stm322399
    Senior
    May 12, 2015
    Posted on May 12, 2015 at 09:33

    I mean that in the case you have a problem with refresh, then observing data in SDRAM will lead to bit corruption evenly in any 16-bit word.

    After some delay:

    d0003d4 fe117206

    After a longer delay:

    d0003d4 fee5fafe

    After a more longer delay:

    d0003d4 ffffffff

    Depending the DRAM technology, some pages tends to fill with 1's others with 0's

    Your example only showed bits D13/14 to be corrupted. Given that DRAM expect tight timings, wiring issues are not excluded (unbalanced capacitive load, long wires, bad grounding, etc...). Normally SDRAM are easy to wire (compared to DDRs), so I assume that the wiring issue should be (more or less) trivial to find. Carefully check pin sharing, pull-up/down, etc ...

    jacekborko
    Associate II
    May 12, 2015
    Posted on May 12, 2015 at 13:36

    after first change of value it looks like:

    Adress   value

    ------

    2002ffe4 cccccccc

    d0000000 eccceccc

    and after couple minutes

    2002ffe4 cccccccc

    d0000000 fcccfccc

    when i connected the D13 or D14 pins to the 0 or 1 i saw just additional change in two place  ( fccXfccX ) and the X changed for example in that way:

      00

      11

      22

      33

      40

      51

      62

      73

      88

      99

      aa

      bb

      c8

      d9

      ea

      fb

    so maybe  that is not a problem with D13 or D14 pins ?

    jacekborko
    Associate II
    May 14, 2015
    Posted on May 14, 2015 at 08:53

    anyone have some suggestions ?