STM32F4 SPI Communication - Last MISO Bit not received

[thomas239955_st]

Posted on October 15, 2014 at 10:33

Hello,

I use a STM32F4-DISCOVERY Board in master mode, which should communicate with a slave via SPI. Basically, the communication is working, but the last bit on the MISO line is always lost. For example, if I receive 0x2E1F (as you can see in the attached picture, purple is MISO, blue is CLK), which would be correct, the STM32F4 recognizes it as 0x2E1E, the last bit is wrong. I tried this with multiple requests, same result. The LSB is always seen as 0.

MOSI data is correct. Clock polarity is also correct.

Has anybody of you already experienced similar problems or has an idea of how to fix this?

Greetings

Thomas

P.S.: The rather complex code is because i tried to split the data word into 2 Bytes for transmission, hoping it would fix my problem, but the result stays the same.

#stm32f4-spi-miso

[waclawek.jan]

Posted on October 15, 2014 at 10:53

Similar symptoms were described at https://my.st.com/public/STe2ecommunities/mcu/Lists/cortex_mx_stm32/Flat.aspx?RootFolder=%2fpublic%2fSTe2ecommunities%2fmcu%2fLists%2fcortex%5fmx%5fstm32%2fSTM32%20SPI%20Spoiled%20Bits&FolderCTID=0x01200200770978C69A1141439FE559EB459D7580009C4E14902C3CDE46A77F0FFD06506F5B&TopicsView=https%3A%2F%2Fmy%2Est%2Ecom%2Fpublic%2FSTe2ecommunities%2Fmcu%2FLists%2Fcortex%5Fmx%5Fstm32%2FAllItems%2Easpx%3FPaged%3DTRUE%26p%5FStickyPost%3D%26p%5FDiscussionLastUpdated%3D20141010%252021%253a14%253a50%26p%5FID%3D46804%26View%3D%257bF47A9ED8%252dE726%252d42BE%252dACED%252d732F13B66581%257d%26FolderCTID%3D0x012001%26PageFirstRow%3D41&currentviews=64

but that thread never came to a decisive conclusion

JW

[waclawek.jan]

Posted on October 15, 2014 at 15:04

Could this be the same problem?

https://my.st.com/public/STe2ecommunities/mcu/Lists/cortex_mx_stm32/Flat.aspx?RootFolder=https%3a%2f%2fmy.st.com%2fpublic%2fSTe2ecommunities%2fmcu%2fLists%2fcortex_mx_stm32%2fSTM32L053%20Nucleo%20-%20SPI%20Issue&FolderCTID=0x01200200770978C69A1141439FE559EB459D7580009C4E14902C3CDE46A77F0FFD06506F5B&currentviews=8

Please post the content of all SPI registers.

JW

[thomas239955_st]

Posted on October 15, 2014 at 15:13

Thank you very much!

Haven't figured out what it was yet, but after reading your first link, I also tried to use SPI2 port instead instead of SPI1 and now it works correctly!

Seems like there is a general problem with SPI1 in these cases...

[alibabashack]

Posted on September 01, 2016 at 12:36

I experienced the exact same behaviour. I am a bit disappointed that this hardware bug is not part of the STM32F42xx and STM32F43xx Errata Sheet. However, I just realized that the problem and possible solutions are given in the STM32F373xx Errata Sheet in section 2.4.5 ''Last data bit or CRC calculation may be corrupted for the data received in SPI/I2S master mode depending on the feedback communication clock timing with respect to the APB clock''.

PLEASE add this to the STM32F42xx and STM32F43xx Errata Sheet to spare your costumers gritting their teeth. Its not that bad to admit there is a bug.

[Amel NASRI]

Posted on September 27, 2016 at 12:17

Hi,

I agree that this SPI related limitation is missing in the F4 errata sheets. It will be added in new versions of this document.

Thank you for highlighting the issue, and Sorry for any inconvenience it may bring for you.

-STM32 Forums Moderator