stm32f4 CAN Filter FIFO assignment?

[Curtis.Allen]

Posted on November 08, 2016 at 04:48

Hello,

1. When creating a CAN filter, what is a reasonable strategy for FIFO assignment? 

2. What happens when the same filter is assigned to both FIFOs?

I am modifying an existing code base and the previous author always assigns the same filter to both FIFOs. Does this mean if the FIFO is full it will automatically start using the other FIFO?

TIA

#!stm32-!can-!can-filtering

[jpeacock23]

Posted on November 08, 2016 at 10:17

The reason for two FIFOs is to prioritize incoming CAN messages.  Messages arrive in order but the protocol used with CAN determines which messages should be processed first, regardless of when they arrive.  For instance, a high priority device failure message should be processed as soon as it arrives, since it may involve safety, or prevention of damage to equipment.  Whatever protocol you use (J1939, DeviceNET, CANopen, etc.) will specify which groups of messages (selected by filters) to route to the high priority FIFO.

The net stack should be designed to drain the high priority FIFO first, queuing those messages ahead of the low priority FIFO for processing by the message listener.  That's why there are two interrupts for RX, assign a higher NVIC priority to the FIFO with high priority traffic.

If you have no priority then it makes no difference which FIFO is used, but that is wasting a key feature of the CAN bus.

  Jack Peacock