STM32F373 Overrun error with SDADC using DMA

[garyconner9]

Posted on June 06, 2013 at 13:44

I am using the both SDADCs configured as follows:

3 channels configured for injected conversions

SDADC2 triggered when SDADC1 is triggered

SDADC1 triggered from timer configured for 200 usec

Both SDADC1 and 2 configured to transfer data via DMA.

All appears to function properly except that random Overrun errors occur anywhere from 2 seconds to 2 minutes apart.  (Timing determined using the ITM trace feature with timestamps.)

Anyone have any idea why overrun error would occur when using DMA?

Thanks

#stm32f73-sdadc-dma

[raptorhal2]

Posted on June 06, 2013 at 16:08

Be more specific about the number of channels being converted by each SDADC. Is it 3 on each, or 2 on one and 1 on the other ?

Check the data sheet to see if you are exceeding or close to the sampling rate limit.

Cheers, Hal

[garyconner9]

Posted on June 06, 2013 at 17:23

Converting 3 Channels on each SDADC.  Each SDADC uses a separate DMA channel.  Each conversion requires 60 usec.  Triggering the injected conversion every 250 usec (original post incorrect).  That leave 70 usec spare. 

Per the user manual, the JOVRF flag is set indicates ''that an injected conversion finished shile the JEOCF was already 1.''  That would mean that the DMA took over 60 usec to read the JDATAR register.  I could not find any specifications on the latency of the DMA transfer, but 60 usec seems like an eternity for a DMA transfer.

[raptorhal2]

Posted on June 06, 2013 at 22:46

I presume you looked at Figure 22 in the reference manual, and something like DAC1 or DAC2 is not occasionally tying up the DMA channel.

Perhaps we can spot something if you post the code.

Cheers, Hal