STM32F2xx SPI DMA FIFO error

[jpeacock2399]

Posted on September 25, 2012 at 00:36

When I use DMA on the transmit SPI2 chanel (STM32F205) I consistently get FIFO errors at the end of the transfer, even though the FIFO is disabled.  I verified the DMDIS flag is 0 in the DMA_SxFCR register but the DMA_HISR register still shows FEIF4 flag set.  DMA stream 4 is configured as a dummy SPI clock, no memory or peripheral increment.  Memory and peripheral burst is set to singular (byte).  FIFO is disabled, threshold set to 1/4.

From what I read in the reference manual it should not be possible to get a FIFO error if the FIFO is disabled, yet it still happens.  It doesn't affect transfers but is a mystery.  Has anyone encountered the same situation?

  Jack Peacock

#spi-dma-fifo

[mario23]

Posted on May 13, 2014 at 16:08

Dear Jack,

Have you ever found a solution to this? I'm have the exact same scenario / behaviour as you, but on a STM32F207.

Mario

[waclawek.jan]

Posted on May 14, 2014 at 08:48

This is considered normal. Simply ignore the FIFO error, if you use Direct mode.

https://my.st.com/public/STe2ecommunities/mcu/Lists/cortex_mx_stm32/Flat.aspx?RootFolder=/public/STe2ecommunities/mcu/Lists/cortex_mx_stm32/DMA+and+Direct+Mode&FolderCTID=0x01200200770978C69A1141439FE559EB459D7580009C4E14902C3CDE46A77F0FFD06506F5B&currentviews=146

JW

[Amel NASRI]

Posted on June 11, 2014 at 15:30

Hi Mario,

Are you enabling the used peripheral before the corresponding DMA stream? If it is the case, a ''FEIF'' may be set. (please refer to AN4031/p32: Using the STM32F2 and STM32F4 DMA controller for more details).

-Mayla-

[jpeacock2399]

Posted on June 11, 2014 at 15:55

What the reference manual doesn't make clear is the FIFO error is also triggered by falling below the FIFO threshold.

  Jack Peacock